STM32MP13 SRAM internal memory

This message will disappear after all relevant tasks have been resolved.

Semantic MediaWiki

There are 1 incomplete or pending task to finish installation of Semantic MediaWiki. An administrator or user with sufficient rights can complete it. This should be done before adding new data to avoid inconsistencies.

Applicable for

STM32MP13x lines

1 Article purpose[edit source]

The purpose of this article is to:

briefly introduce the SRAM internal memory peripheral and its main features,
indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
list the software frameworks and drivers managing the peripheral,
explain how to configure the peripheral.

2 Peripheral overview[edit source]

The SRAM peripheral is 32-Kbyte wide, split into three separate banks:

SRAM1 (16 Kbytes)
SRAM2 (8 Kbytes)
SRAM3 (8 Kbytes)

Those banks have individual security control (see security support in the runtime assignment table below) and automatic clock gating (for power management optimization), but they are not supplied when the system goes to Standby low power mode, so their content is lost in that case.

Refer to the STM32MP13 reference manuals for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.

3 Peripheral usage[edit source]

This chapter is applicable in the scope of the OpenSTLinux BSP running on the Arm^® Cortex^®-A processor(s), and the STM32CubeMPU Package running on the Arm^® Cortex^®-M processor.

3.1 Boot time assignment[edit source]

3.1.1 On STM32MP13x lines [edit source]

The ROM code uses:

the SRAM1 and SRAM2 to store internal data
the SRAM3 to store the FSBL header

This ROM code mapping strategy aims to leave the whole SYSRAM internal memory free for FSBL binary loading then execution.

The TF-A BL2 uses:

the SRAM1 to store boot NAND 4kB scratch buffer
the SRAM2 to store MbedTLS in case of secure boot
the SRAM3 to store fw-config DT

Click on the right to expand the legend...

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

☐ means that the peripheral can be assigned to the given boot time context.
☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32 MPU reference manuals.

Domain	Peripheral	Boot time allocation				Comment
Domain	Peripheral	Instance	Cortex-A7 secure (ROM code)	Cortex-A7 secure (TF-A BL2)	Cortex-A7 non-secure (U-Boot)	Comment
Core/RAM	SRAM	Any instance	✓	☑	☐	SRAM first used by ROM code, then TF-A BL2. After assignment free to user

3.2 Runtime assignment[edit source]

3.2.1 On STM32MP13x lines [edit source]

Click on the right to expand the legend...

STM32MP13 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

☐ means that the peripheral can be assigned to the given runtime context.
☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP13 reference manuals.

Domain	Peripheral	Runtime allocation			Comment
Domain	Peripheral	Instance	Cortex-A7 secure (OP-TEE)	Cortex-A7 non-secure (Linux)	Comment
Core/RAM	SRAM	SRAM1	☐	☐	Assignment (between A7 S and A7 NS)
		SRAM2	☐	☐	Assignment (between A7 S and A7 NS)
		SRAM3	☐	☐	Assignment (between A7 S and A7 NS)

4 Software frameworks and drivers[edit source]

Below are listed the software frameworks and drivers managing the XXX peripheral for the embedded software components listed in the above tables.

Linux^®: reserved memory, that is used by the dmaengine (for DMA buffers management)
OP-TEE: OP-TEE
TF-A BL2: TF-A BL2

5 How to assign and configure the peripheral[edit source]

The peripheral assignment can be done via the STM32CubeMX graphical tool (and manually completed if needed).
This tool also helps to configure the peripheral:

partial device trees (pin control and clock tree) generation for the OpenSTLinux software components,
HAL initialization code generation for the STM32CubeMPU Package.

The configuration is applied by the firmware running in the context in which the peripheral is assigned.