Difference between revisions of "SDMMC internal peripheral"

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1 Article purpose[edit]

The purpose of this article is to

  • briefly introduce the SDMMC peripheral and its main features
  • indicate the level of security supported by this hardware block
  • explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
  • explain, when needednecessary, how to configure the SDMMC peripheral.

2 Peripheral overview[edit]

The SDMMC peripheral is used to interconnect STM32 MPU to SD memory cards, SDIO and MMC devices.

2.1 Features[edit]

Refer to the STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to know see which features are really implemented.

2.2 Security support[edit]

SDMMC1/2/3 instances are either non-secure or secure peripherals (under ETZPC control).

Warning.png
  • When an SDMMC instance is secure internal, the DMA cannot be used to perform data transfers.
  • STMicroelectronics does not provide secure MMC driver (see below chapter)

3 Peripheral usage and associated software[edit]

3.1 Boot time[edit]

SDMMC1/2 instances can be used to support memory boot on SD or MMC Flash devices.

The SDMMC3 is not used at boot time.

Info.png The SDMMC instances are ordered by address in the device tree arch/arm/boot/dts/stm32mp151.dtsi file:
sdmmc3: sdmmc@48004000 {
...
sdmmc1: sdmmc@58005000 {
...
sdmmc2: sdmmc@58007000 {

By default, in OpenSTLinux distribution, sdmmc3 is disabled so the sdmmc1 (SD card on Evaluation boards and Discovery kits) and sdmmc2 (eMMC on Evaluation boards and Wifi on Discovery kits) are respectively aliased to mmc0 and mmc1.
If you enable sdmmc3, it will take the mmc0 alias and the aliases above will shift, so don't forget to update the Linux kernel boot command accordingly!
For instance, 'root=/dev/mmcblk0p6' will become 'root=/dev/mmcblk1p6' to mount the rootfs from the sdmmc1 (SD card) when sdmmc3 is enabled.

3.2 Runtime[edit]

3.2.1 Overview[edit]

SDMMC1/2/3 instances can be allocated to:

  • the Arm® Cortex®-A7 non-secure core to be used under controlled in Linux® with by the MMC framework

or

Chapter #Peripheral assignment describes which peripheral instance can be assigned to which context.

3.2.2 Software frameworks[edit]

Domain Peripheral Software frameworks Comment
Cortex-A7
secure
(OP-TEE)
Cortex-A7
non-secure
(Linux)
Cortex-M4

(STM32Cube)
Mass storage SDMMC Linux MMC framework STM32Cube SDMMC driver

3.2.3 Peripheral configuration[edit]

The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration by itself can be performed done alone via the STM32CubeMX tool for all internal peripherals. It can , and then be manually completed (especially particularly for external peripherals), according to the information given in the corresponding software framework article.

For Linux® kernel configuration, please refer to SDMMC device tree configuration.

3.2.4 Peripheral assignment[edit]

Internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

  • means that the peripheral can be assigned () to the given runtime context.
  • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain Peripheral Runtime allocation Comment
Instance Cortex-A7
secure
(OP-TEE)
Cortex-A7
non-secure
(Linux)
Cortex-M4

(STM32Cube)
Mass storage SDMMC SDMMC1
SDMMC2
SDMMC3 Assignment (single choice)

4 How to go further[edit]

Chapter not applicable right now, maybe completed later.

5 References[edit]

Chapter not applicable right now, maybe completed later.




<noinclude>

{{ArticleBasedOnModel| [[Internal peripheral article model]]}}
{{ArticleMainWriter|LudovicB}}
{{ArticleApprovedVersion| LudovicB | GeraldB, ChristopheK,NathalieS, YannG  | No previous approved version | AnneJ - 06Aug'18 - 8316 | 03Sep'18}}

[[Category:High speed interface peripherals]]
[[Category:Mass storage peripherals]]

{{ReviewsComments|JCT 1840: alignment needed with the last version of the model [[Internal peripheral article model]]<br>

[[Category:ToBeAlignedWithModel]]
}}</noinclude>

==Article purpose==
The purpose of this article is to
* briefly introduce the SDMMC peripheral and its main features
* indicate the level of security supported by this hardware block
* explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
* explain, when needednecessary, how to configure the SDMMC peripheral.

==Peripheral overview==
The '''SDMMC''' peripheral is used to interconnect STM32 MPU to SD memory cards, SDIO and MMC devices.

===Features===
Refer to the [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software components, introduced below, to knowsee which features are really implemented.

===Security support===
SDMMC1/2/3 instances are either '''non-secure''' or '''secure''' peripherals (under [[ETZPC_internal_peripheral|ETZPC]] control).

{{Warning|
* When an SDMMC instance is secure internal, the DMA cannot be used to perform data transfers. 
* STMicroelectronics does not provide secure MMC driver (see below chapter)}}

==Peripheral usage and associated software==
===Boot time===
SDMMC1/2 instances can be used to support memory boot on SD or MMC Flash devices.

The SDMMC3 is not used at boot time.

===Runtime==={{Info | The SDMMC instances are ordered by address in the [[Device tree|device tree]] {{CodeSource | Linux kernel | arch/arm/boot/dts/stm32mp151.dtsi}} file:
 sdmmc3: sdmmc@48004000 {
 ...
 sdmmc1: sdmmc@58005000 {
 ...
 sdmmc2: sdmmc@58007000 {
By default, in [[OpenSTLinux distribution]], '''sdmmc3 is disabled''' so the sdmmc1 (SD card on [[STM32MP157x-EV1_-_hardware_description|Evaluation boards]] and [[STM32MP157x-DKx_-_hardware_description|Discovery kits]]) and sdmmc2 (eMMC on [[STM32MP157x-EV1_-_hardware_description|Evaluation boards]] and Wifi on [[STM32MP157x-DKx_-_hardware_description|Discovery kits]]) are respectively aliased to mmc0 and mmc1.<br>

'''If you enable sdmmc3''', it will take the mmc0 alias and the aliases above will shift, so don't forget to update the Linux kernel boot command accordingly!<br>

For instance, 'root&#61;/dev/mmcblk0p6' will become 'root&#61;/dev/mmcblk1p6' to mount the rootfs from the sdmmc1 (SD card) when sdmmc3 is enabled.}}

===Runtime===
====Overview====
SDMMC1/2/3 instances can be allocated to:
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure core to be used undercontrolled in Linux<sup>&reg;</sup> withby the [[MMC overview|MMC framework]]or* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-M4 to be used withcontrolled in STM32Cube MPU Package withby [[STM32CubeMP1 architecture|STM32Cube SDMMC driver]]
Chapter [[#Peripheral assignment]] describes which peripheral instance can be assigned to which context.

====Software frameworks====
{{:Internal_peripherals_software_table_template}}
 | Mass storage
 | [[SDMMC internal peripheral|SDMMC]]
 | 
 | [[MMC overview|Linux MMC framework]]
 | [[STM32CubeMP1 architecture|STM32Cube SDMMC driver]]
 |
 |-
 |}

====Peripheral configuration====
The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration by itself can be performed done alone via the [[STM32CubeMX]] tool for all internal peripherals. It can then be manually completed (especially for external peripherals), and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article.

For Linux<sup>&reg;</sup> kernel configuration, please refer to [[SDMMC device tree configuration]].

====Peripheral assignment====
{{:Internal_peripherals_assignment_table_template}}<onlyinclude>

 | rowspan="3" | Mass storage
 | rowspan="3" | [[SDMMC internal peripheral|SDMMC]]
 | SDMMC1
 | 
 | <span title="assignable peripheral" style="font-size:21px"></span>

 |
 |
 |-
 | SDMMC2
 | 
 | <span title="assignable peripheral" style="font-size:21px"></span>

 | 
 |
 |-
 | SDMMC3
 | 
 | <span title="assignable peripheral" style="font-size:21px"></span>

 | <span title="assignable peripheral" style="font-size:21px"></span>

 | Assignment (single choice)
 |-</onlyinclude>

 |}

==How to go further==Chapter not applicable right now, maybe completed later.

==References==
Chapter not applicable right now, maybe completed later.<references/>

==References==<references/>

<noinclude>

{{ArticleBasedOnModel | Internal peripheral article model}}
{{PublicationRequestId | 8316 | 2018-08-06 | AnneJ}}
[[Category:High speed interface peripherals]]
[[Category:Mass storage peripherals]]</noinclude>
(16 intermediate revisions by 4 users not shown)
Line 1: Line 1:
<noinclude>
 
{{ArticleBasedOnModel| [[Internal peripheral article model]]}}
 
{{ArticleMainWriter|LudovicB}}
 
{{ArticleApprovedVersion| LudovicB | GeraldB, ChristopheK,NathalieS, YannG  | No previous approved version | AnneJ - 06Aug'18 - 8316 | 03Sep'18}}
 
 
[[Category:High speed interface peripherals]]
 
[[Category:Mass storage peripherals]]
 
 
{{ReviewsComments|JCT 1840: alignment needed with the last version of the model [[Internal peripheral article model]]<br>
 
[[Category:ToBeAlignedWithModel]]
 
}}
 
</noinclude>
 
 
 
==Article purpose==
 
==Article purpose==
 
The purpose of this article is to
 
The purpose of this article is to
Line 17: Line 4:
 
* indicate the level of security supported by this hardware block
 
* indicate the level of security supported by this hardware block
 
* explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
 
* explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
* explain, when needed, how to configure the SDMMC peripheral.
+
* explain, when necessary, how to configure the SDMMC peripheral.
   
 
==Peripheral overview==
 
==Peripheral overview==
Line 23: Line 10:
   
 
===Features===
 
===Features===
Refer to [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software components, introduced below, to know which features are really implemented.
+
Refer to the [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software components, introduced below, to see which features are implemented.
   
 
===Security support===
 
===Security support===
Line 37: Line 24:
   
 
The SDMMC3 is not used at boot time.
 
The SDMMC3 is not used at boot time.
  +
{{Info | The SDMMC instances are ordered by address in the [[Device tree|device tree]] {{CodeSource | Linux kernel | arch/arm/boot/dts/stm32mp151.dtsi}} file:
  +
sdmmc3: sdmmc@48004000 {
  +
...
  +
sdmmc1: sdmmc@58005000 {
  +
...
  +
sdmmc2: sdmmc@58007000 {
  +
By default, in [[OpenSTLinux distribution]], '''sdmmc3 is disabled''' so the sdmmc1 (SD card on [[STM32MP157x-EV1_-_hardware_description|Evaluation boards]] and [[STM32MP157x-DKx_-_hardware_description|Discovery kits]]) and sdmmc2 (eMMC on [[STM32MP157x-EV1_-_hardware_description|Evaluation boards]] and Wifi on [[STM32MP157x-DKx_-_hardware_description|Discovery kits]]) are respectively aliased to mmc0 and mmc1.<br>
  +
'''If you enable sdmmc3''', it will take the mmc0 alias and the aliases above will shift, so don't forget to update the Linux kernel boot command accordingly!<br>
  +
For instance, 'root&#61;/dev/mmcblk0p6' will become 'root&#61;/dev/mmcblk1p6' to mount the rootfs from the sdmmc1 (SD card) when sdmmc3 is enabled.}}
   
 
===Runtime===
 
===Runtime===
  +
 
====Overview====
 
====Overview====
 
SDMMC1/2/3 instances can be allocated to:
 
SDMMC1/2/3 instances can be allocated to:
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure core to be used under Linux<sup>&reg;</sup> with the [[MMC overview|MMC framework]]
+
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure core to be controlled in Linux<sup>&reg;</sup> by the [[MMC overview|MMC framework]]
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-M4 to be used with STM32Cube MPU Package with [[STM32CubeMP1 architecture|STM32Cube SDMMC driver]]
+
or
  +
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-M4 to be controlled in STM32Cube MPU Package by [[STM32CubeMP1 architecture|STM32Cube SDMMC driver]]
 
Chapter [[#Peripheral assignment]] describes which peripheral instance can be assigned to which context.
 
Chapter [[#Peripheral assignment]] describes which peripheral instance can be assigned to which context.
   
Line 57: Line 55:
   
 
====Peripheral configuration====
 
====Peripheral configuration====
The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration by itself can be performed via the [[STM32CubeMX]] tool for all internal peripherals. It can then be manually completed (especially for external peripherals) according to the information given in the corresponding software framework article.
+
The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the [[STM32CubeMX]] tool for all internal peripherals, and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article.
   
 
For Linux<sup>&reg;</sup> kernel configuration, please refer to [[SDMMC device tree configuration]].
 
For Linux<sup>&reg;</sup> kernel configuration, please refer to [[SDMMC device tree configuration]].
Line 88: Line 86:
   
 
==How to go further==
 
==How to go further==
Chapter not applicable right now, maybe completed later.
 
   
 
==References==
 
==References==
Chapter not applicable right now, maybe completed later.
 
 
<references/>
 
<references/>
  +
  +
<noinclude>
  +
{{ArticleBasedOnModel | Internal peripheral article model}}
  +
{{PublicationRequestId | 8316 | 2018-08-06 | AnneJ}}
  +
[[Category:High speed interface peripherals]]
  +
[[Category:Mass storage peripherals]]
  +
</noinclude>