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Difference between revisions of "RETRAM internal memory"
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Contents
1 Peripheral overview[edit]
The RETRAM internal memory is 64 Kbytes wide and is physically near to the Arm® Cortex®-M4 for optimized performance from the core. It is located in the VSW power domain, allowing it to be supplied during Standby low power mode, and to retain retention firmware that can be executed very quickly by the Cortex-M4 on wake up from Standby mode.
1.1 Features[edit]
Refer to STM32MP15 reference manuals for the complete feature list, and to the software components introduced below to see which features are actually implemented.
1.2 Security support[edit]
The RETRAM is a secure peripheral (under ETZPC control).
2 Peripheral usage and associated software[edit]
2.1 Boot time[edit]
Linux® remoteproc framework (running on the Cortex-A7) loads the Cortex-M4 firmware to the RETRAM, starting at address 0x00000000. At least, it must load the part of the firmware containing the vector table, since the Cortex-M4 reset entry point is address 0x00000004. The rest of the firmware code is loaded into the MCU SRAM. The overall memory mapping is shown in the platform memory mapping section.
2.2 Runtime[edit]
2.2.1 Overview[edit]
The Cortex-M4 vector table is mapped from address 0x00000000 (so to the RETRAM) at reset, but it can be remapped by software to any other location by means of the vector table offset register (VTOR). Beyond the reset entry point (0x00000004), the exception table also contains the software entries table used by the NVIC to branch the software execution to the right interrupt service routine.
While going to Standby low power mode, the RETRAM can remain supplied, so it can preserve a (small) Cortex-M4 piece of retention firmware that is executed on wake up when the ROM code (running on Cortex-A7) restarts the Cortex-M4.
All these constraints make the RETRAM the minimum (and default) choice for Cortex-M4 firmware.
RETRAM can be allocated to:
- the Cortex-A7 secure to be used under OP-TEE.
or
- the Cortex-A7 non-secure to be used under Linux as reserved memory.
or
- the Cortex-M4 for use with the STM32Cube MPU Package, either for runtime firmware that ca be mapped in both RETRAM and MCU SRAM, or for retention firmware that only fits into the RETRAM, but could have some data in MCU SRAM (keeping in mind that these data are lost while entering Standby low power mode).
2.2.2 Software frameworks[edit]
Internal peripherals software table template
|| Domain | Peripheral | Software components | Comment | ||
|---|---|---|---|---|---|
| OP-TEE | Linux | STM32Cube | |||
| Core/RAM | |||||
| RETRAM | OP-TEE |
| overview |
| Linux |
| reserved |
| memory |
| STM32Cube |
2.2.3 Peripheral configuration[edit]
The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the STM32CubeMX tool for all internal peripherals, and then manually completed (especially for external peripherals), according to the information given in the corresponding software framework article.
2.2.4 Peripheral assignment[edit]
Internal peripherals assignment table template
| rowspan="1" | Core/RAM | rowspan="1" | RETRAM | RETRAM | ☐ | ☐ | ☐ | Assignment (single choice) |-
|}
3 How to go further[edit]
4 References[edit]
Click on the right to expand the legend...
Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:
- ☐ means that the peripheral can be assigned (☑) to the given runtime context.
- ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
- ✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.
Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.
| Domain | Peripheral | Runtime allocation | Comment | |||
|---|---|---|---|---|---|---|
| Instance |
Cortex-A7
secure (OP-TEE) |
Cortex-A7
non-secure (Linux) |
Cortex-M4
(STM32Cube) |
|||
| Core/RAM | RETRAM | RETRAM | ☐ | ☐ | ☐ | Assignment (single choice) |
<noinclude> {{ArticleBasedOnModel | [[Internal peripheral article model]]}} {{ArticleMainWriter | GeraldB}} {{ArticleApprovedVersion | GeraldB | FrancoisC, ArnaudP, NathalieS | No previous approved version| PhilipS - 29aug'18 - 8334 | 4Sep'18}} [[Category:RAM interfaces]] {{ReviewsComments|JCT 1840: alignment needed with the last version of the model [[Internal peripheral article model]]<br> [[Category:ToBeAlignedWithModel]] }}</noinclude> {{ApplicableFor |MPUs list=STM32MP15x |MPUs checklist=STM32MP13x, STM32MP15x }}</noinclude> ==Peripheral overview== The '''RETRAM''' internal memory is 64 Kbytes wide and is physically near to the Arm<sup>®</sup> Cortex<sup>®</sup>-M4 for optimized performance from the core. It is located in the VSW power domain, allowing it to be supplied during Standby [[Power overview|low power mode]], and to retain retention firmware that can be executed very quickly by the Cortex-M4 on wake up from Standby mode. ===Features=== Refer to [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete feature list, and to the software components introduced below to see which features are actually implemented.<br> ===Security support=== The RETRAM is a '''secure ''' peripheral (under [[ETZPC_internal_peripheral|ETZPC]] control). ==Peripheral usage and associated software== ===Boot time=== [[Linux remoteproc framework overview|Linux<sup>®</sup> remoteproc framework]] (running on the Cortex-A7) loads the Cortex-M4 firmware to the RETRAM, starting at address 0x00000000. At least, it must load the part of the firmware containing the vector table, since the Cortex-M4 reset entry point is address 0x00000004. The rest of the firmware code is loaded into the [[STM32MP15 MCU SRAM internal memory|MCU SRAM]]. The overall memory mapping is shown in the platform [[STM32MP15_RAM_mapping#Zoom in the Cortex-A7/Cortex-M4 shared memory |memory mapping]] section. ===Runtime=== ====Overview==== The Cortex-M4 vector table is mapped from address 0x00000000 (so to the RETRAM) at reset, but it can be remapped by software to any other location by means of the vector table offset register (VTOR). Beyond the reset entry point (0x00000004), the exception table also contains the software entries table used by the [[NVIC internal peripheral|NVIC]] to branch the software execution to the right interrupt service routine.<br /> <br> While going to Standby [[Power overview|low power mode]], the RETRAM can remain supplied, so it can preserve a (small) Cortex-M4 piece of retention firmware that is executed on wake up when the [[STM32MP15 STM32 MPU ROM code overview|ROM code]] (running on Cortex-A7) restarts the Cortex-M4. <br> All these constraints make the RETRAM the minimum (and default) choice for Cortex-M4 firmware.<br> RETRAM can be allocated to: * the Cortex-A7 secure to be used under [[OP-TEE overview|OP-TEE]]. or * the Cortex-A7 non-secure to be used under Linux as [[Reserved memory|reserved memory]]. or * the Cortex-M4 for use with the STM32Cube MPU Package, either for '''runtime firmware''' that ca be mapped in both RETRAM and [[STM32MP15 MCU SRAM internal memory|MCU SRAM]], or for '''retention firmware''' that only fits into the RETRAM, but could have some data in [[STM32MP15 MCU SRAM internal memory|MCU SRAM]] (keeping in mind that these data are lost while entering Standby [[Power overview|low power mode]]). ====Software frameworks==== {{:Internal_STM32MP15_internal_peripherals_software_table_template}} | Core/RAM | [[RETRAM internal memory|RETRAM]] | [[OP-TEE_overview|OP-TEE overview]] | [[Reserved memory|Linux reserved memory]] | [[STM32CubeMP1 architecture|STM32Cube]] | |- |} ====Peripheral configuration==== The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the [[STM32CubeMX]] tool for all internal peripherals, and then manually completed (especially for external peripherals), according to the information given in the corresponding software framework article. ====Peripheral assignment==== {{:Internal_STM32MP15_internal_peripherals_assignment_table_template}}<onlyinclude> | rowspan="1" | Core/RAM | rowspan="1" | [[RETRAM internal memory|RETRAM]] | RETRAM | <span title="assignable peripheral" style="font-size:21px">☐</span> | <span title="assignable peripheral" style="font-size:21px">☐</span> | <span title="assignable peripheral" style="font-size:21px">☐</span> | Assignment (single choice) |-</onlyinclude> |} ==How to go further== ==References==<references/><noinclude> [[Category:RAM interfaces]] {{PublicationRequestId | 8334 | 2018-08-29 | PhilipS}} {{ArticleBasedOnModel | Internal peripheral article model}} {{ReviewsComments|JCT 1840: alignment needed with the last version of the model<br> [[Category:ToBeAlignedWithModel]] }}</noinclude>
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==Peripheral overview== |
==Peripheral overview== |
||
The '''RETRAM''' internal memory is 64 Kbytes wide and is physically near to the Arm<sup>®</sup> Cortex<sup>®</sup>-M4 for optimized performance from the core. It is located in the VSW power domain, allowing it to be supplied during Standby [[Power overview|low power mode]], and to retain retention firmware that can be executed very quickly by the Cortex-M4 on wake up from Standby mode. |
The '''RETRAM''' internal memory is 64 Kbytes wide and is physically near to the Arm<sup>®</sup> Cortex<sup>®</sup>-M4 for optimized performance from the core. It is located in the VSW power domain, allowing it to be supplied during Standby [[Power overview|low power mode]], and to retain retention firmware that can be executed very quickly by the Cortex-M4 on wake up from Standby mode. |
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| Line 20: | Line 13: | ||
==Peripheral usage and associated software== |
==Peripheral usage and associated software== |
||
===Boot time=== |
===Boot time=== |
||
| − | [[Linux remoteproc framework overview|Linux<sup>®</sup> remoteproc framework]] (running on the Cortex-A7) loads the Cortex-M4 firmware to the RETRAM, starting at address 0x00000000. At least, it must load the part of the firmware containing the vector table, since the Cortex-M4 reset entry point is address 0x00000004. The rest of the firmware code is loaded into the [[MCU SRAM internal memory|MCU SRAM]]. The overall memory mapping is shown in the platform [[STM32MP15_RAM_mapping#Zoom in the Cortex-A7/Cortex-M4 shared memory |memory mapping]] section. |
+ | [[Linux remoteproc framework overview|Linux<sup>®</sup> remoteproc framework]] (running on the Cortex-A7) loads the Cortex-M4 firmware to the RETRAM, starting at address 0x00000000. At least, it must load the part of the firmware containing the vector table, since the Cortex-M4 reset entry point is address 0x00000004. The rest of the firmware code is loaded into the [[STM32MP15 MCU SRAM internal memory|MCU SRAM]]. The overall memory mapping is shown in the platform [[STM32MP15_RAM_mapping#Zoom in the Cortex-A7/Cortex-M4 shared memory |memory mapping]] section. |
===Runtime=== |
===Runtime=== |
||
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The Cortex-M4 vector table is mapped from address 0x00000000 (so to the RETRAM) at reset, but it can be remapped by software to any other location by means of the vector table offset register (VTOR). Beyond the reset entry point (0x00000004), the exception table also contains the software entries table used by the [[NVIC internal peripheral|NVIC]] to branch the software execution to the right interrupt service routine.<br /> |
The Cortex-M4 vector table is mapped from address 0x00000000 (so to the RETRAM) at reset, but it can be remapped by software to any other location by means of the vector table offset register (VTOR). Beyond the reset entry point (0x00000004), the exception table also contains the software entries table used by the [[NVIC internal peripheral|NVIC]] to branch the software execution to the right interrupt service routine.<br /> |
||
<br> |
<br> |
||
| − | While going to Standby [[Power overview|low power mode]], the RETRAM can remain supplied, so it can preserve a (small) Cortex-M4 piece of retention firmware that is executed on wake up when the [[ |
+ | While going to Standby [[Power overview|low power mode]], the RETRAM can remain supplied, so it can preserve a (small) Cortex-M4 piece of retention firmware that is executed on wake up when the [[STM32 MPU ROM code overview|ROM code]] (running on Cortex-A7) restarts the Cortex-M4. |
<br> |
<br> |
||
All these constraints make the RETRAM the minimum (and default) choice for Cortex-M4 firmware. |
All these constraints make the RETRAM the minimum (and default) choice for Cortex-M4 firmware. |
||
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* the Cortex-A7 non-secure to be used under Linux as [[Reserved memory|reserved memory]]. |
* the Cortex-A7 non-secure to be used under Linux as [[Reserved memory|reserved memory]]. |
||
or |
or |
||
| − | * the Cortex-M4 for use with the STM32Cube MPU Package, either for '''runtime firmware''' that ca be mapped in both RETRAM and [[MCU SRAM internal memory|MCU SRAM]], or for '''retention firmware''' that only fits into the RETRAM, but could have some data in [[MCU SRAM internal memory|MCU SRAM]] (keeping in mind that these data are lost while entering Standby [[Power overview|low power mode]]). |
+ | * the Cortex-M4 for use with the STM32Cube MPU Package, either for '''runtime firmware''' that ca be mapped in both RETRAM and [[STM32MP15 MCU SRAM internal memory|MCU SRAM]], or for '''retention firmware''' that only fits into the RETRAM, but could have some data in [[STM32MP15 MCU SRAM internal memory|MCU SRAM]] (keeping in mind that these data are lost while entering Standby [[Power overview|low power mode]]). |
====Software frameworks==== |
====Software frameworks==== |
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+ | {{:STM32MP15_internal_peripherals_software_table_template}} |
| Core/RAM |
| Core/RAM |
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| [[RETRAM internal memory|RETRAM]] |
| [[RETRAM internal memory|RETRAM]] |
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====Peripheral assignment==== |
====Peripheral assignment==== |
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| − | {{: |
+ | {{:STM32MP15_internal_peripherals_assignment_table_template}} |
<onlyinclude> |
<onlyinclude> |
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| rowspan="1" | Core/RAM |
| rowspan="1" | Core/RAM |
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