QUADSPI internal peripheral

Applicable for STM32MP13x lines, STM32MP15x lines

1 Article purpose[edit]

The purpose of this article is to

  • briefly introduce the QUADSPI peripheral and its main features
  • indicate the level of security supported by this hardware block
  • explain how each instance can be allocated to the runtime contexts and linked to the corresponding software components
  • explain, when needed, how to configure the QUADSPI peripheral.

2 Peripheral overview[edit]

The Quad-SPI interface (QUADSPI peripheral) is used to interface the processor with serial NOR Flash and serial NAND Flash memories.
It supports:

  • Single, dual or quad SPI Flash memories
  • A dual-flash mode, allowing to agregate two Flash memories into a virtual single one
  • Dual data rate and memory-mapped modes.

2.1 Features[edit]

Refer to STM32MP13 reference manuals or STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to know which features are really implemented.

2.2 Security support[edit]

2.2.1 On STM32MP13x lines Warning.png[edit]

The QUADSPI is a secure peripheral (under ETZPC control).

2.2.2 On STM32MP15x lines More info.png[edit]

The QUADSPI is a non secure peripheral.

3 Using the peripheral - associated software[edit]

3.1 Boot time[edit]

QUADSPI instance is boot device that support serial boot for Flash programming with STM32CubeProgrammer.

3.2 Runtime[edit]

3.2.1 Overview[edit]

The QUADSPI instances can be allocated to:

  • the Arm® Cortex®-A7 secure context, on STM32MP13x lines Warning.png only, but this is not supported in OpenSTLinux.

or

  • the Arm® Cortex®-A7 non-secure core to be controlled in Linux® by the MTD framework

or

  • the Arm® Cortex®-M4, on STM32MP15x lines More info.png only, to be controlled in STM32Cube MPU Package by QUADSPI HAL driver

Chapter #Peripheral assignment describes which peripheral instances can be assigned to which context.

3.2.2 Software frameworks[edit]

3.2.2.1 On STM32MP13x lines Warning.png[edit]
Domain Peripheral Software components Comment
OP-TEE Linux
Mass storage QUADSPI Linux MTD framework
3.2.2.2 On STM32MP15x lines More info.png[edit]
Domain Peripheral Software components Comment
OP-TEE Linux STM32Cube
Mass storage QUADSPI Linux MTD framework STM32Cube QUADSPI driver

3.2.3 Peripheral configuration[edit]

The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the STM32CubeMX tool for all internal peripherals, and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article.

For Linux kernel configuration, please refer to QUADSPI device tree configuration.

3.2.4 Peripheral assignment[edit]

3.2.4.1 On STM32MP13x lines Warning.png[edit]

Click on the right to expand the legend...

STM32MP13IPsOverview.png

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

  • means that the peripheral can be assigned () to the given runtime context.
  • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
  • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP13 reference manuals.

Domain Peripheral Runtime allocation Comment
Instance Cortex-A7
secure
(OP-TEE)
Cortex-A7
non-secure
(Linux)
Mass storage QUADSPI QUADSPI Assignment (single choice)
3.2.4.2 On STM32MP15x lines More info.png[edit]

Click on the right to expand the legend...

STM32MP15 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

  • means that the peripheral can be assigned () to the given runtime context.
  • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
  • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain Peripheral Runtime allocation Comment
Instance Cortex-A7
secure
(OP-TEE)
Cortex-A7
non-secure
(Linux)
Cortex-M4

(STM32Cube)
Mass storage QUADSPI QUADSPI Assignment (single choice)

4 References[edit]