Difference between revisions of "QUADSPI device tree configuration"

[quality revision] [quality revision]
m
 
Applicable for STM32MP13x lines, STM32MP15x lines

1 Article purpose[edit]

This article explains The purpose of this article is to explain how to configure the QUADSPI internal peripheral when it is assigned to the Linux® OS. In that case, it is controlled by the MTD framework. The configuration is performed using the device tree mechanism that provides a hardware , relying on the bindings documentation, that is the description of the QUADSPI peripheral, used by the STM32 QUADSPI Linux driver and by the MTD framework. If the peripheral is assigned to another execution context, refer required and optional device-tree properties.

The peripheral can be assigned to different contexts/software components, depending on the final product needs. Refer to How to assign an internal peripheral to a runtime context article for guidelines on peripheral assignment and this configuration.

2 DT bindings documentation[edit]

The QUADSPI device tree bindings are composed by:

generic

binding documents are stored either in the given applicable components listed below, or in the Linux kernel repository:

  • TF-A BL2, U-Boot, OP-TEE, Linux® OS:
    • Generic SPI-NOR / SPI-NAND Flash memory
    bindings [1].
  • QUADSPI driver bindings [2].
In next chapters, SPI-NAND bindings are only compatible with ecosystem release ≥ v1.1.0 .

3 DT configuration[edit]

This hardware description is a combination of the STM32 microprocessor device tree files (.dtsi extension) and board device tree files (.dts extension). See the Device tree for an explanation of the device-tree file splitorganization.

STM32CubeMX can be used to generate the board device tree. Refer to How to configure the DT using STM32CubeMX for more details.

3.1 DT configuration (STM32 level)[edit]

The QUADSPI peripheral node is located in stm32mp157c.dtsi[3] filethe device tree file for the software components, supporting the peripheral and listed in the above DT bindings documentation paragraph.

Warning white.png Warning
This device tree part is related to STM32 microprocessors. It must be kept as is, without being modified by the end-user.

3.2 DT configuration (board level)[edit]

The objective of this chapter is to explain how to enable and configure the QUADSPI DT nodes for a board.

Peripheral configuration should be done in specific board device tree files (board dts file and pinctrl dtsi file).

   
&qspi: spi@58003000 {                                      Comments        compatible = "st,stm32f469-qspi";   Comments
    reg = <0x58003000 0x1000>,pinctrl-names = "default", "sleep";                         --> RegisterFor locationpinctrl configuration, please refer to Pinctrl device tree configuration
     <0x70000000 0x10000000>; pinctrl-0 = <&qspi_clk_test_pins_a
                    --> Memory mapping address
       reg-names = "qspi", "qspi_mm";
       interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;&qspi_bk1_test_pins_b
       --> The interrupt number used        dmas = <&mdma1 22 0x10 0x100002 0x0 0x0 0x0>,&qspi_cs1_test_pins_b
              --> DMA specifiers [4]            <&mdma1 22 0x10 0x100008 0x0 0x0 0x0>;&qspi_bk2_test_pins_b
             dma-names = "tx", "rx";        clocks = <&rcc QSPI_K>&qspi_cs2_test_pins_b>;
       resetspinctrl-1 = <&rcc QSPI_R>;qspi_clk_test_sleep_pins_a
          status = "disabled";    };  
Warning white.png Warning
This device tree part related to the STM32 should be kept as is, the customer should not modify it.
3.2 DT configuration (board level)[edit]

The QUADSPI peripheral may connect a maximum of 2 SPI-NOR Flash memories.

SPI-NOR Flash memory nodes [1] must be children of the QUADSPI peripheral node.

  
 &qspi {_bk1_test_sleep_pins_b
                    &qspi_cs1_test_sleep_pins_b
                              Comments
       pinctrl-names = "default", "sleep";&qspi_bk2_test_sleep_pins_b
                  --> For pinctrl configuration, please refer to Pinctrl device tree configuration
       pinctrl-0 = <&qspi_clkcs2_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
       pinctrl-1 = <&qspi_clk_test_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>b>;
       reg = <0x58003000 0x1000>,
             <0x70000000 0x4000000>;                         --> Overwrite the memory map to the Flash device size, avoid the waste of virtual memory that will not be used
       #address-cells = <1>;
       #size-cells = <0>;
       status = "okay";                                      --> Enable the node

flash0: mx66l51235l@0 { compatible = "jdecjedec,spi-nor"; reg = <0>; --> Chip select number spi-rx-bus-width = <4>; --> The bus width (number of data wires used) spi-max-frequency = <108000000>; --> Maximum SPI clocking speed of device in Hz #address-cells = <1>; #size-cells = <1>; }; };

3.3 DT configuration example[edit]

The below example shows how to configure the QUADSPI peripheral when 1 SPI-NAND Flash and 1 SPI-NOR Flash memories are connected.

   &qspi {                                                    
       pinctrl-names = "default", "sleep";                    
       pinctrl-0 = <&qspi_clk_test_pins_a
                    &qspi_bk1_test_pins_a &qspi_bk2_pins_a>b
                    &qspi_cs1_test_pins_b
                    &qspi_bk2_test_pins_b
                    &qspi_cs2_test_pins_b>;
       pinctrl-1 = <&qspi_clk_test_sleep_pins_a
                    &qspi_bk1_test_sleep_pins_a &qspi_bk2_sleep_pins_a>b
                    &qspi_cs1_test_sleep_pins_b
                    &qspi_bk2_test_sleep_pins_b
                    &qspi_cs2_test_sleep_pins_b>;
       reg = <0x58003000 0x1000>,
             <0x70000000 0x4000000>;                          
       #address-cells = <1>;
       #size-cells = <0>;
       status = "okay";
flash0: mx66l51235l@0 { compatible = "jdecjedec,spi-nor"; reg = <0>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; #address-cells = <1>; #size-cells = <1>; };
flash1: mt29f2g01abagd@1 { compatible = "spi-nand"; reg = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; spi-max-frequency = <133000000>; #address-cells = <1>; #size-cells = <1>; }; };

The below example, possible with ecosystem release ≥ v4.1.0 More info.png , shows how to configure the QUADSPI peripheral to use it as a communication channel using up to 8 qspi lines. It can be used to communicate with a FPGA. To enable the usage of the 8 qspi lines, the following properties are mandatory:

  • the chip select pins need to be removed from pinctrl-0 and pinctrl-1 properties.
  • cs-gpios properties must be populated in the controller node.
  • spi-rx-bus-width and spi-tx-bus-width properties must be set to 8 in the device node.
   &qspi {                                                    
       pinctrl-names = "default", "sleep";                    
       pinctrl-0 = <&qspi_clk_test_pins_a
                    &qspi_bk1_test_pins_b
                    &qspi_bk2_test_pins_b>;
       pinctrl-1 = <&qspi_clk_test_sleep_pins_a
                    &qspi_bk1_test_sleep_pins_b
                    &qspi_bk2_test_sleep_pins_b>;
       reg = <0x58003000 0x1000>,
             <0x70000000 0x4000000>;                          
       #address-cells = <1>;
       #size-cells = <0>;
       status = "okay";
       cs-gpios = <&gpiob 6 GPIO_ACTIVE_LOW>;

fpga@0 { compatible = "fpga"; reg = <0>; spi-rx-bus-width = <8>; spi-tx-bus-width = <8>; spi-max-frequency = <108000000>; #address-cells = <1>; #size-cells = <1>; }; };

4 How to configure the DT using STM32CubeMX[edit]

The STM32CubeMX tool can be used to configure the STM32MPU device and get the corresponding platform configuration device tree files.
The STM32CubeMX may not support all the properties described in DT binding files listed in the above DT bindings documentation paragraph. If so, the tool inserts user sections in the generated device tree. These sections can then be edited to add some properties, and they are preserved from one generation to another. Refer to STM32CubeMX user manual for further information.

5 References[edit]

Please refer Refer to the following links for full description:

additional information:




== Article purpose ==
This article explains <noinclude>{{ApplicableFor
|MPUs list=STM32MP13x, STM32MP15x
|MPUs checklist=STM32MP13x,STM32MP15x
}}</noinclude>


== Article purpose ==
The purpose of this article is to explain how to configure the [[QUADSPI internal peripheral|'''QUADSPI''' internal peripheral]] when it is assigned to the Linux<sup>&reg;</sup> OS. In that case, it is controlled by the  [[MTD overview|MTD framework]].

The configuration is performed ]] using the [[Device tree|device tree]] mechanism that provides a hardware description of the QUADSPI peripheral, used by the STM32 QUADSPI Linux driver and by  the MTD framework.

If the peripheral is assigned to another execution context, refer , relying on the bindings documentation, that is the description of the required and optional device-tree properties.

The peripheral can be assigned to different contexts/software components, depending on the final product needs. Refer to [[How to assign an internal peripheral to a runtime context]] article for guidelines on peripheral assignment and this configuration.

== DT bindings documentation ==
The QUADSPI device tree bindings binding documents are composed by:

* generic stored either in the given applicable components listed below, or in the Linux kernel repository: <br>


* TF-A BL2, U-Boot, OP-TEE, Linux<sup>&reg;</sup> OS:
** Generic SPI-NOR / SPI-NAND Flash memory device tree bindings <ref name="spi_busses_bindings">: {{CodeSource | Linux kernel | Documentation/devicetree/bindings/spi/spi-bus.txt}}</ref>.

* QUADSPI driver bindings <ref> controller.yaml}}.
** QUADSPI device tree bindings: {{CodeSource | Linux kernel | Documentation/devicetree/bindings/spi/spi-st,stm32-qspi.txt}} </ref>.

In next chapters, SPI-NAND bindings are only compatible with {{EcosystemRelease | revision=1.1.0 | range=and after}}.

== yaml}}.

== DT configuration ==
This hardware description is a combination of the '''STM32 microprocessor''' device tree files (''.dtsi'' extension) and '''board''' device tree files (''.dts'' extension). See the [[Device tree]] for an explanation of the device -tree file splitorganization.

'''STM32CubeMX''' can be used to generate the board device tree. Refer to [[#How_to_configure_the_DT_using_STM32CubeMX|How to configure the DT using STM32CubeMX]] for more details.

===DT configuration (STM32 level) ===
The QUADSPI peripheral node is located in ''stm32mp157c.dtsi''<ref>{{CodeSource | Linux kernel | arch/arm/boot/dts/stm32mp157c.dtsi}}</ref> file. 

    qspi: spi@58003000 {                                      {{highlight|Comments}}
        compatible = "st,stm32f469-qspi";
        reg = <0x58003000 0x1000>,                            {{highlight|--> Register location}}<0x70000000 0x10000000>;                        {{highlight|--> Memory mapping address}}
        reg-names = "qspi", "qspi_mm";
        interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;        {{highlight|--> The interrupt number used}}
        dmas = <&mdma1 22 0x10 0x100002 0x0 0x0 0x0>,         {{highlight|--> DMA specifiers <ref>{{CodeSource | Linux kernel | Documentation/devicetree/bindings/dma/stm32-mdma.txt}}</ref>}}<&mdma1 22 0x10 0x100008 0x0 0x0 0x0>;
        dma-names = "tx", "rx";
        clocks = <&rcc QSPI_K>;
        resets = <&rcc QSPI_R>;   
        status = "disabled";
    };

{{Warning|This device tree part related to the STM32 should be kept as is, the customer should not modify it.}}

=== DT configuration (board level) ===
The QUADSPI peripheral may connect a maximum of 2 SPI-NOR Flash memories.

SPI-NOR Flash memory nodes <ref name="spi_busses_bindings"/> must be children of the QUADSPI peripheral node.
the [[STM32 MPU device_tree#Device tree structure|device tree file]] for the software components, supporting the peripheral and listed in the above [[#DT bindings documentation|DT bindings documentation]] paragraph.

{{Warning|This device tree part is related to STM32 microprocessors. It must be kept as is, without being modified by the end-user.}}

=== DT configuration (board level) ===
The objective of this chapter is to explain how to enable and configure the QUADSPI DT nodes for a board.

Peripheral configuration should be done in specific board device tree files (board dts file  and [[Pinctrl device tree configuration|pinctrl  dtsi file]]).
&qspi {                                                   {{highlight|Comments}}
        pinctrl-names = "default", "sleep";                   {{highlight|--> For pinctrl configuration, please refer to [[Pinctrl device tree configuration]]}}
        pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a><&qspi_clk_test_pins_a
                     &qspi_bk1_test_pins_b
                     &qspi_cs1_test_pins_b
                     &qspi_bk2_test_pins_b
                     &qspi_cs2_test_pins_b>;
        pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a><&qspi_clk_test_sleep_pins_a
                     &qspi_bk1_test_sleep_pins_b
                     &qspi_cs1_test_sleep_pins_b
                     &qspi_bk2_test_sleep_pins_b
                     &qspi_cs2_test_sleep_pins_b>;
        reg = <0x58003000 0x1000>,<0x70000000 0x4000000>;                         {{highlight|--> Overwrite the memory map to the Flash device size, avoid the waste of virtual memory that will not be used}}
        #address-cells = <1>;
        #size-cells = <0>;
        status = "okay";                                      {{highlight|--> Enable the node}}<br>

        flash0: mx66l51235l@0 {     
            compatible = "jdecjedec,spi-nor";                                  
            reg = <0>;                                        {{highlight|--> Chip select number}}
            spi-rx-bus-width = <4>;                           {{highlight|--> The bus width (number of data wires used)}}
            spi-max-frequency = <108000000>;                  {{highlight|--> Maximum SPI clocking speed of device in Hz}}
            #address-cells = <1>;
            #size-cells = <1>;
        };
    };

=== DT configuration example ===
The below example shows how to configure the QUADSPI peripheral when 1 SPI-NAND Flash and 1 SPI-NOR Flash memories are connected.

    &qspi {                                                    
        pinctrl-names = "default", "sleep";                    
        pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a><&qspi_clk_test_pins_a
                     &qspi_bk1_test_pins_b
                     &qspi_cs1_test_pins_b
                     &qspi_bk2_test_pins_b
                     &qspi_cs2_test_pins_b>;
        pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a><&qspi_clk_test_sleep_pins_a
                     &qspi_bk1_test_sleep_pins_b
                     &qspi_cs1_test_sleep_pins_b
                     &qspi_bk2_test_sleep_pins_b
                     &qspi_cs2_test_sleep_pins_b>;
        reg = <0x58003000 0x1000>,<0x70000000 0x4000000>;                          
        #address-cells = <1>;
        #size-cells = <0>;
        status = "okay";<br>

        flash0: mx66l51235l@0 {                                 
            compatible = "jdecjedec,spi-nor";
            reg = <0>;
            spi-rx-bus-width = <4>;
            spi-max-frequency = <108000000>;
            #address-cells = <1>;
            #size-cells = <1>;
        };<br>

        flash1: mt29f2g01abagd@1 {                             
            compatible = "spi-nand";
            reg = <1>;
            spi-rx-bus-width = <4>;
            spi-tx-bus-width = <4>;
            spi-max-frequency = <133000000>;
            #address-cells = <1>;
            #size-cells = <1>;
        };
    };
==The below example, possible with {{EcosystemRelease | revision =4.1.0 |range = and after}},  shows how to configure the QUADSPI peripheral to use it as a communication channel using up to 8 qspi lines. It can be used to communicate with a FPGA.
To enable the usage of the 8 qspi lines, the following properties are mandatory:
* the chip select pins need to be removed from pinctrl-0 and pinctrl-1 properties.
* cs-gpios properties must be populated in the controller node.
* spi-rx-bus-width and spi-tx-bus-width properties must be set to 8 in the device node.

    &qspi {                                                    
        pinctrl-names = "default", "sleep";                    
        pinctrl-0 = <&qspi_clk_test_pins_a
                     &qspi_bk1_test_pins_b
                     &qspi_bk2_test_pins_b>;
        pinctrl-1 = <&qspi_clk_test_sleep_pins_a
                     &qspi_bk1_test_sleep_pins_b
                     &qspi_bk2_test_sleep_pins_b>;
        reg = <0x58003000 0x1000>,<0x70000000 0x4000000>;                          
        #address-cells = <1>;
        #size-cells = <0>;
        status = "okay";
        cs-gpios = <&gpiob 6 GPIO_ACTIVE_LOW>;<br>

        fpga@0 {                                 
            compatible = "fpga";
            reg = <0>;
            spi-rx-bus-width = <8>;
            spi-tx-bus-width = <8>;
            spi-max-frequency = <108000000>;
            #address-cells = <1>;
            #size-cells = <1>;
        };
    };

==How to configure the DT using STM32CubeMX==
The [[STM32CubeMX]] tool can be used to configure the STM32MPU device and get the corresponding [[Device_tree#STM32_MPU|platform configuration device tree]] files.<br />
The STM32CubeMX may not support all the properties described in DT binding files listed in the above [[#DT bindings documentation|DT bindings documentation]] paragraph. If so, the tool inserts '''user sections''' in the generated device tree. These sections can then be edited to add some properties, and they are preserved from one generation to another. Refer to [[STM32CubeMX]] user manual for further information.

==References==Please refer Refer to the following links for full description:
additional information:<references />

<noinclude>

{{ArticleBasedOnModel | Peripheral or framework device tree configuration model}}
{{PublicationRequestId | 8899 |2018-10-10 |  AlainF}}
[[Category:Device tree configuration]]
[[Category:Mass storage]]</noinclude>
(13 intermediate revisions by 4 users not shown)
Line 1: Line 1:
  +
<noinclude>{{ApplicableFor
  +
|MPUs list=STM32MP13x, STM32MP15x
  +
|MPUs checklist=STM32MP13x,STM32MP15x
  +
}}</noinclude>
  +
 
== Article purpose ==
 
== Article purpose ==
This article explains how to configure the [[QUADSPI internal peripheral|'''QUADSPI''' internal peripheral]] when it is assigned to the Linux<sup>&reg;</sup> OS. In that case, it is controlled by the  [[MTD overview|MTD framework]].
+
The purpose of this article is to explain how to configure the [[QUADSPI internal peripheral|'''QUADSPI''']] using the [[Device tree|device tree]] mechanism, relying on the bindings documentation, that is the description of the required and optional device-tree properties.
   
The configuration is performed using the [[Device tree|device tree]] mechanism that provides a hardware description of the QUADSPI peripheral, used by the STM32 QUADSPI Linux driver and by  the MTD framework.
+
The peripheral can be assigned to different contexts/software components, depending on the final product needs. Refer to [[How to assign an internal peripheral to a runtime context]] article for guidelines on this configuration.
 
 
If the peripheral is assigned to another execution context, refer to [[How to assign an internal peripheral to a runtime context]] article for guidelines on peripheral assignment and configuration.
 
   
 
== DT bindings documentation ==
 
== DT bindings documentation ==
  +
The device tree binding documents are stored either in the given applicable components listed below, or in the Linux kernel repository: <br>
   
The QUADSPI device tree bindings are composed by:
+
* TF-A BL2, U-Boot, OP-TEE, Linux<sup>&reg;</sup> OS:
 
+
** Generic SPI-NOR / SPI-NAND Flash memory device tree bindings: {{CodeSource | Linux kernel | Documentation/devicetree/bindings/spi/spi-controller.yaml}}.
* generic SPI-NOR / SPI-NAND Flash memory bindings <ref name="spi_busses_bindings">{{CodeSource | Linux kernel | Documentation/devicetree/bindings/spi/spi-bus.txt}}</ref>.
+
** QUADSPI device tree bindings: {{CodeSource | Linux kernel | Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml}}.
 
 
* QUADSPI driver bindings <ref> {{CodeSource | Linux kernel | Documentation/devicetree/bindings/spi/spi-stm32-qspi.txt}} </ref>.
 
 
 
In next chapters, SPI-NAND bindings are only compatible with {{EcosystemRelease | revision=1.1.0 | range=and after}}.
 
   
 
== DT configuration ==
 
== DT configuration ==
This hardware description is a combination of the '''STM32 microprocessor''' device tree files (''.dtsi'' extension) and '''board''' device tree files (''.dts'' extension). See the [[Device tree]] for an explanation of the device tree file split.
+
This hardware description is a combination of the '''STM32 microprocessor''' device tree files (''.dtsi'' extension) and '''board''' device tree files (''.dts'' extension). See the [[Device tree]] for an explanation of the device-tree file organization.
   
 
'''STM32CubeMX''' can be used to generate the board device tree. Refer to [[#How_to_configure_the_DT_using_STM32CubeMX|How to configure the DT using STM32CubeMX]] for more details.
 
'''STM32CubeMX''' can be used to generate the board device tree. Refer to [[#How_to_configure_the_DT_using_STM32CubeMX|How to configure the DT using STM32CubeMX]] for more details.
   
 
===DT configuration (STM32 level) ===
 
===DT configuration (STM32 level) ===
The QUADSPI peripheral node is located in ''stm32mp157c.dtsi''<ref>{{CodeSource | Linux kernel | arch/arm/boot/dts/stm32mp157c.dtsi}}</ref> file.  
+
The QUADSPI node is located in the [[STM32 MPU device_tree#Device tree structure|device tree file]] for the software components, supporting the peripheral and listed in the above [[#DT bindings documentation|DT bindings documentation]] paragraph.
   
    qspi: spi@58003000 {                                      {{highlight|Comments}}
+
{{Warning|This device tree part is related to STM32 microprocessors. It must be kept as is, without being modified by the end-user.}}
        compatible = "st,stm32f469-qspi";
 
        reg = <0x58003000 0x1000>,                            {{highlight|--> Register location}}
 
              <0x70000000 0x10000000>;                        {{highlight|--> Memory mapping address}}
 
        reg-names = "qspi", "qspi_mm";
 
        interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;        {{highlight|--> The interrupt number used}}
 
        dmas = <&mdma1 22 0x10 0x100002 0x0 0x0 0x0>,        {{highlight|--> DMA specifiers <ref>{{CodeSource | Linux kernel | Documentation/devicetree/bindings/dma/stm32-mdma.txt}}</ref>}}
 
              <&mdma1 22 0x10 0x100008 0x0 0x0 0x0>;
 
        dma-names = "tx", "rx";
 
        clocks = <&rcc QSPI_K>;
 
        resets = <&rcc QSPI_R>; 
 
        status = "disabled";
 
    };
 
 
{{Warning|This device tree part related to the STM32 should be kept as is, the customer should not modify it.}}
 
   
 
=== DT configuration (board level) ===
 
=== DT configuration (board level) ===
The QUADSPI peripheral may connect a maximum of 2 SPI-NOR Flash memories.
+
The objective of this chapter is to explain how to enable and configure the QUADSPI DT nodes for a board.
   
SPI-NOR Flash memory nodes <ref name="spi_busses_bindings"/> must be children of the QUADSPI peripheral node.
+
Peripheral configuration should be done in specific board device tree files (board dts file  and [[Pinctrl device tree configuration|pinctrl  dtsi file]]).
   
 
     &qspi {                                                  {{highlight|Comments}}
 
     &qspi {                                                  {{highlight|Comments}}
 
         pinctrl-names = "default", "sleep";                  {{highlight|--> For pinctrl configuration, please refer to [[Pinctrl device tree configuration]]}}
 
         pinctrl-names = "default", "sleep";                  {{highlight|--> For pinctrl configuration, please refer to [[Pinctrl device tree configuration]]}}
         pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
+
         pinctrl-0 = <&qspi_clk_test_pins_a
         pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>;
+
                    &qspi_bk1_test_pins_b
  +
                    &qspi_cs1_test_pins_b
  +
                    &qspi_bk2_test_pins_b
  +
                    &qspi_cs2_test_pins_b>;
  +
         pinctrl-1 = <&qspi_clk_test_sleep_pins_a
  +
                    &qspi_bk1_test_sleep_pins_b
  +
                    &qspi_cs1_test_sleep_pins_b
  +
                    &qspi_bk2_test_sleep_pins_b
  +
                    &qspi_cs2_test_sleep_pins_b>;
 
         reg = <0x58003000 0x1000>,
 
         reg = <0x58003000 0x1000>,
 
               <0x70000000 0x4000000>;                        {{highlight|--> Overwrite the memory map to the Flash device size, avoid the waste of virtual memory that will not be used}}
 
               <0x70000000 0x4000000>;                        {{highlight|--> Overwrite the memory map to the Flash device size, avoid the waste of virtual memory that will not be used}}
Line 55: Line 49:
 
         status = "okay";                                      {{highlight|--> Enable the node}}<br>
 
         status = "okay";                                      {{highlight|--> Enable the node}}<br>
 
         flash0: mx66l51235l@0 {     
 
         flash0: mx66l51235l@0 {     
             compatible = "jdec,spi-nor";                                   
+
             compatible = "jedec,spi-nor";                                   
 
             reg = <0>;                                        {{highlight|--> Chip select number}}
 
             reg = <0>;                                        {{highlight|--> Chip select number}}
 
             spi-rx-bus-width = <4>;                          {{highlight|--> The bus width (number of data wires used)}}
 
             spi-rx-bus-width = <4>;                          {{highlight|--> The bus width (number of data wires used)}}
Line 69: Line 63:
 
     &qspi {                                                     
 
     &qspi {                                                     
 
         pinctrl-names = "default", "sleep";                     
 
         pinctrl-names = "default", "sleep";                     
         pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
+
         pinctrl-0 = <&qspi_clk_test_pins_a
         pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>;
+
                    &qspi_bk1_test_pins_b
  +
                    &qspi_cs1_test_pins_b
  +
                    &qspi_bk2_test_pins_b
  +
                    &qspi_cs2_test_pins_b>;
  +
         pinctrl-1 = <&qspi_clk_test_sleep_pins_a
  +
                    &qspi_bk1_test_sleep_pins_b
  +
                    &qspi_cs1_test_sleep_pins_b
  +
                    &qspi_bk2_test_sleep_pins_b
  +
                    &qspi_cs2_test_sleep_pins_b>;
 
         reg = <0x58003000 0x1000>,
 
         reg = <0x58003000 0x1000>,
 
               <0x70000000 0x4000000>;                           
 
               <0x70000000 0x4000000>;                           
Line 77: Line 79:
 
         status = "okay";<br>
 
         status = "okay";<br>
 
         flash0: mx66l51235l@0 {                                 
 
         flash0: mx66l51235l@0 {                                 
             compatible = "jdec,spi-nor";
+
             compatible = "jedec,spi-nor";
 
             reg = <0>;
 
             reg = <0>;
 
             spi-rx-bus-width = <4>;
 
             spi-rx-bus-width = <4>;
Line 90: Line 92:
 
             spi-tx-bus-width = <4>;
 
             spi-tx-bus-width = <4>;
 
             spi-max-frequency = <133000000>;
 
             spi-max-frequency = <133000000>;
  +
            #address-cells = <1>;
  +
            #size-cells = <1>;
  +
        };
  +
    };
  +
  +
The below example, possible with {{EcosystemRelease | revision =4.1.0 |range = and after}},  shows how to configure the QUADSPI peripheral to use it as a communication channel using up to 8 qspi lines. It can be used to communicate with a FPGA.
  +
To enable the usage of the 8 qspi lines, the following properties are mandatory:
  +
* the chip select pins need to be removed from pinctrl-0 and pinctrl-1 properties.
  +
* cs-gpios properties must be populated in the controller node.
  +
* spi-rx-bus-width and spi-tx-bus-width properties must be set to 8 in the device node.
  +
  +
    &qspi {                                                   
  +
        pinctrl-names = "default", "sleep";                   
  +
        pinctrl-0 = <&qspi_clk_test_pins_a
  +
                    &qspi_bk1_test_pins_b
  +
                    &qspi_bk2_test_pins_b>;
  +
        pinctrl-1 = <&qspi_clk_test_sleep_pins_a
  +
                    &qspi_bk1_test_sleep_pins_b
  +
                    &qspi_bk2_test_sleep_pins_b>;
  +
        reg = <0x58003000 0x1000>,
  +
              <0x70000000 0x4000000>;                         
  +
        #address-cells = <1>;
  +
        #size-cells = <0>;
  +
        status = "okay";
  +
        cs-gpios = <&gpiob 6 GPIO_ACTIVE_LOW>;<br>
  +
        fpga@0 {                               
  +
            compatible = "fpga";
  +
            reg = <0>;
  +
            spi-rx-bus-width = <8>;
  +
            spi-tx-bus-width = <8>;
  +
            spi-max-frequency = <108000000>;
 
             #address-cells = <1>;
 
             #address-cells = <1>;
 
             #size-cells = <1>;
 
             #size-cells = <1>;
Line 96: Line 129:
   
 
==How to configure the DT using STM32CubeMX==
 
==How to configure the DT using STM32CubeMX==
The [[STM32CubeMX]] tool can be used to configure the STM32MPU device and get the corresponding [[Device_tree#STM32|platform configuration device tree]] files.<br />
+
The [[STM32CubeMX]] tool can be used to configure the STM32MPU device and get the corresponding [[Device_tree#STM32_MPU|platform configuration device tree]] files.<br />
The STM32CubeMX may not support all the properties described in the above [[#DT bindings documentation|DT bindings documentation]] paragraph. If so, the tool inserts '''user sections''' in the generated device tree. These sections can then be edited to add some properties and they are preserved from one generation to another. Refer to [[STM32CubeMX]] user manual for further information.
+
STM32CubeMX may not support all the properties described in DT binding files listed in the above [[#DT bindings documentation|DT bindings documentation]] paragraph. If so, the tool inserts '''user sections''' in the generated device tree. These sections can then be edited to add some properties, and they are preserved from one generation to another. Refer to [[STM32CubeMX]] user manual for further information.
   
 
==References==
 
==References==
Please refer to the following links for full description:
+
Refer to the following links for additional information:
 
 
 
<references />
 
<references />