Difference between revisions of "NVIC internal peripheral"

[quality revision] [quality revision]
(Merge articles)
m
 

1 Article purpose[edit]

The purpose of this article is to:

  • briefly introduce the NVIC and its main features
  • indicate the level of security supported by this hardware block
  • explain how the NVIC can be configured.

2 Peripheral overview[edit]

The NVIC is the Arm® Cortex®-M4 interrupt controller. As a result, it cannot be accessed by the Arm Cortex-A7 core.

2.1 Features[edit]

Refer to STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to see which features are implemented.

2.2 Security support[edit]

The NVIC is a non-secure peripheral.

3 Peripheral usage and associated software[edit]

3.1 Boot time[edit]

The NVIC can be configured through the STM32Cube.

3.2 Runtime[edit]

3.2.1 Overview[edit]

The NVIC can be allocated only to the Arm Cortex-M4 core to be controlled in the STM32Cube by the NVIC HAL driver.

3.2.2 Software frameworks[edit]

Internal peripherals software table template

|
Domain Peripheral Software components Comment
OP-TEE Linux STM32Cube
Core/Interrupts
| NVIC | | | STM32Cube NVIC driver | |- |}
NVIC STM32Cube NVIC driver

3.2.3 Peripheral configuration[edit]

The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the STM32CubeMX tool for all internal peripherals, and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article.

3.2.4 Peripheral assignment[edit]

Internal peripherals assignment table template

| rowspan="1" | Core/Interrupts
| rowspan="1" | NVIC
| NVIC
| 
|
| 
|
|-

|}

Click on the right to expand the legend...

STM32MP15 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

  • means that the peripheral can be assigned () to the given runtime context.
  • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
  • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain Peripheral Runtime allocation Comment
Instance Cortex-A7
secure
(OP-TEE)
Cortex-A7
non-secure
(Linux)
Cortex-M4

(STM32Cube)
Core/Interrupts NVIC NVIC



==Article purpose==
The purpose of this article is to:
* briefly introduce the NVIC and its main features
* indicate the level of security supported by this hardware block
* explain how the NVIC can be configured.

==Peripheral overview==
The '''NVIC''' is the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-M4 interrupt controller. As a result, it cannot be accessed by the Arm Cortex-A7 core.

===Features===
Refer to [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software components, introduced below, to see which features are implemented.<br>


===Security support===
The NVIC is a '''non-secure''' peripheral.

==Peripheral usage and associated software==
===Boot time===
The NVIC can be configured through the [[STM32CubeMP1 architecture|STM32Cube]]. 

===Runtime===
====Overview====
The NVIC can be allocated only to the Arm Cortex-M4 core to be controlled in the STM32Cube by the [[STM32CubeMP1 architecture|NVIC HAL driver]].

====Software frameworks====
{{:Internal_STM32MP15_internal_peripherals_software_table_template}}
 | Core/Interrupts
 | [[NVIC internal peripheral|NVIC]]
 | 
 | 
 | [[STM32CubeMP1 architecture|STM32Cube NVIC driver]]
 |
 |-
 |}

====Peripheral configuration====
The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the [[STM32CubeMX]] tool for all internal peripherals, and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article.

====Peripheral assignment====
{{:Internal_STM32MP15_internal_peripherals_assignment_table_template}}<onlyinclude>

 | rowspan="1" | Core/Interrupts
 | rowspan="1" | [[NVIC internal peripheral|NVIC]]
 | NVIC
 | 
 |
 | <span title="system peripheral" style="font-size:21px"></span>

 |
 |-</onlyinclude>

 |}
<noinclude>

[[Category:Interrupts peripherals]]
{{PublicationRequestId | 8860 | 2018-09-21 | AnneJ}}
{{ArticleBasedOnModel| Internal peripheral article model}}
{{ReviewsComments|JCT 1840: alignment needed with the last version of the model [[Contributors:Internal peripheral article model]]<br>

[[Category:ToBeAlignedWithModel]]
}}</noinclude>
Line 23: Line 23:
   
 
====Software frameworks====
 
====Software frameworks====
{{:Internal_peripherals_software_table_template}}
+
{{:STM32MP15_internal_peripherals_software_table_template}}
 
  | Core/Interrupts
 
  | Core/Interrupts
 
  | [[NVIC internal peripheral|NVIC]]
 
  | [[NVIC internal peripheral|NVIC]]
Line 37: Line 37:
   
 
====Peripheral assignment====
 
====Peripheral assignment====
{{:Internal_peripherals_assignment_table_template}}
+
{{:STM32MP15_internal_peripherals_assignment_table_template}}
 
<onlyinclude>
 
<onlyinclude>
 
  | rowspan="1" | Core/Interrupts
 
  | rowspan="1" | Core/Interrupts