Difference between revisions of "How to change the CPU frequency"

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Applicable for STM32MP13x lines, STM32MP15x lines

1 Purpose[edit]

This article explains how to change the CPU operating point (also known as OPP). An operating point corresponds to the frequency of the processor and the voltage that needs to be supplied to sustain it.
It also shows how it is possible to define multiple operating points, allowing the system to jump among them at run time: this is the dynamic voltage and frequency scaling (DVFS). Some cautions are given at the end of the article, to help the user in its DVFS deployment.

2 Hardware side[edit]

On STM32MP1 Series products, the Cortex-A7 core is:

  • can be clocked by PLL1 from the RCC internal peripheral. The : the PLL1P output frequency can be directly propagated to the core, or it can go through an intermediate MPUDIV divider
  • is supplied with VDDcore voltage.
  • VDDCPU voltage on STM32MP13x lines Warning.png
  • VDDCORE voltage on STM32MP15x lines More info.png

The part number tells which devices can be clocked up to 800 MHzthe device maximum supported frequency, up to 1 GHz for the STM32MP13 or up to 800 MHz for the STM32MP15, with associated usage conditions. Otherwise, the frequency must be kept below 650 MHz.

3 Software side[edit]

3.1 Overview Boot time[edit]

Two ways are offered to the user in order to set the CPU frequency:

By default, in OpenSTLinux distribution, TF-A BL2 sets the CPU frequency to 650 MHz, that is the maximum frequency sustainable with the nominal voltage.

Notice that the processor must receive the nominal voltage during TF-A BL2 execution, whether configuring the STPMIC1 from TF-A BL2 itself or getting it from a discrete power supply, depending on the hardware board configuration.

3.1.1 On STM32MP13x lines Warning.png[edit]

3.1.1.1 VDDCPU voltage configuration[edit]

The example below sets STPMIC1 BUCK1 minimal voltage to 1.25 V, allowing to provide the expected nominal voltage on VDDCPU for the CPU:

  vddcpu: buck1 {
    regulator-name = "vddcpu";
    regulator-min-microvolt = <1250000>;
    ...
};

3.1.1.2 CPU frequency configuration[edit]

TF-A recovers the CPU frequency configuration via the following Clock device tree configuration properties read:

&rcc {
	...
	st,clksrc = <
		CLK_MPU_PLL1P
		... >;

	st,pll_vco {
		...
		pll1_vco_1300Mhz: pll1-vco-1300Mhz {
			src = < CLK_PLL12_HSE >;
			divmn = < 2 80 >;
			frac = < 0x800 >;
		};
	};
	pll1:st,pll@0 {
		...
		st,pll = < &pll1_cfg1 >;
		...
		pll1_cfg1: pll1_cfg1 {
			st,pll_vco = < &pll1_vco_1300Mhz >;
			st,pll_div_pqr = < 0 1 1 >;
		};
	};

3.1.2 On STM32MP15x lines More info.png[edit]

3.1.2.1 VDDCORE voltage configuration[edit]

The example below sets STPMIC1 BUCK1 minimal voltage to 1.2 V, allowing to provide the expected nominal voltage on VDDCORE for the CPU:

  vddcore: buck1 {
    regulator-name = "vddcore";
    regulator-min-microvolt = <1200000>;
    ...
};

3.1.2.2 CPU frequency configuration[edit]

TF-A recovers the CPU frequency configuration via the following Clock device tree configuration properties read:

&rcc {
	...
	/* VCO = 1300.0 MHz => P = 650 (CPU) */
	pll1: st,pll@0 {
		cfg = < 2 80 0 0 0 PQR(1,0,0) >;
		frac = < 0x800 >;
	};
	...
};

3.2 Runtime[edit]

3.2.1 On STM32MP13x lines Warning.png[edit]

3.2.1.1 Overview[edit]

By default, in OpenSTLinux distribution, the OP-TEE "soc extension" device tree file defines an OPP table that contains one or several frequency / voltage pair(s)

  • Nevertheless, it is possible to directly define the expected PLL1 static configuration in the FSBL device tree
  • .

    Info white.png Information
    Whatever the implementation is, if your part number supports up to 800 MHz1 GHz, ensure that the VDDcore VDDCPU minimum voltage is increased from 1.2V 25 V to 1.35 V while running above 650 MHz
    3.2.1.2 OPP table[edit]

    At boot time, TF-A automatically selects the fastest operating point that is suitable for the current part number according to the OPP table (frequency and voltage couples) defined in the SOC extension device tree (fdts/stm32mp15xa.dtsi or fdts/stm32mp15xd.dtsi ).
    At runtime, the Linux will automatically request to OP-TEE SCMI interface to switch between the available operating points according to the CPU load and thanks to Linux cpufreq framework, configured with "ondemand" governor policy (see Documentation/admin-guide/pm/cpufreq.rst ). This feature is called dynamic voltage and frequency scaling (DVFS).

    For instance, in the example below, two operating points ([800 MHz 1 GHz ; 1.35 V]; [400 650 MHz ; 1.2 25 V]) are defined for a 800 MHz 1 GHz capable part number (opp-supported-hw = <0x2>), so TF-A will apply the [800 MHz ; 1.35 V] configuration at boot time and Linux will then dynamically jump between the :

    &cpu0_opp_table {
    		opp-1000000000 {
    			opp-hz = /bits/ 64 <1000000000>;
    			opp-microvolt = <1350000>;
    			opp-supported-hw = <0x2>;
    			st,opp-default;
    		};
    
    		opp-650000000 {
    			opp-hz = /bits/ 64 <650000000>;
    			opp-microvolt = <1250000>;
    			opp-supported-hw = <0x2>;
    		};
    };
    
    

    The PLL1 configurations needed to reach the above frequencies must be described via the 'st,clk_opp' property in 'rcc' device tree node, like this is visible in core/arch/arm/dts/stm32mp135f-dk.dts :

    	st,clk_opp {
    		st,ck_mpu {
    			cfg_1 {
    				hz = < 1000000000 >;
    				st,clksrc = < CLK_MPU_PLL1P >;
    				st,pll = < &pll1_cfg2 >;
    			};
    			cfg_2 {
    				hz = < 650000000 >;
    				st,clksrc = < CLK_MPU_PLL1P >;
    				st,pll = < &pll1_cfg1 >;
    			};
    		};
    	};
    
    

    Notes:

    • The operating point(s) supported by devices able to run above 650 MHz (and up to 1 GHz) is/are identified by the opp-supported-hw property set to 0x2.
    • This description is valid for cold boot, but also when coming back from Standby low power mode.

    3.2.2 On STM32MP15x lines More info.png[edit]

    3.2.2.1 Overview[edit]

    By default, in OpenSTLinux distribution, the Linux kernel "soc extension" device tree file defines an OPP table that contains one or several frequency / voltage pair(s).

    Info white.png Information
    Whatever the implementation is, if your part number supports up to 800 MHz, ensure that the VDDCORE minimum voltage is increased from 1.2 V to 1.35 V while running above 650 MHz
    3.2.2.2 OPP table[edit]

    At runtime, the Linux kernel will automatically switch between the available operating points according to the CPU load and thanks to Linux cpufreq framework, configured with "ondemand" governor policy (see Documentation/admin-guide/pm/cpufreq.rst ). This feature is called dynamic voltage and frequency scaling (DVFS).

    For instance, in the example below, two operating points ([800 MHz ; 1.35 V]; [400 MHz ; 1.2 V]) depending on the CPU load. are defined for a 800 MHz capable part number (opp-supported-hw = <0x2>):

    &cpu0_opp_table {
    		opp-800000000 {
    			opp-hz = /bits/ 64 <800000000>;
    			opp-microvolt = <1350000>;
    			opp-supported-hw = <0x2>;
    		};
    		opp-400000000 {
    			opp-hz = /bits/ 64 <400000000>;
    			opp-microvolt = <1200000>;
    			opp-supported-hw = <0x2>;
    			opp-suspend;
    		};
    };
    
    

    Notes:

    • The operating point(s) supported by devices able to run above 650 MHz (and up to 800 MHz) is/are identified by the opp-supported-hw property set to 0x2.
    • This same OPP table must be present in both the BL32 (either OP-TEE or TF-A SP-MIN) and Linux device tree
    • This description is valid for cold boot, but also when coming back from Standby low power mode.
    • During cold boot, BL32 (either OP-TEE or TF-A SP-MIN) computes and saves the PLL1 settings for all operating points available in the device tree in compliance with the hardware capabilities. These saved paramaters are used later to increase the performance of the system-state transitions.

    3.3 PLL1 static configuration[edit]

    The Cortex-A7 core frequency is selected at boot time, by the FSBL (TF-A), following the Clock device tree configuration - Bootloader specific syntax.

    &rcc { ... /* VCO = 1300.0 MHz => P = 650 (CPU) */ pll1: st,pll@0 { cfg = < 2 80 0 0 0 PQR(1,0,0) >; frac = < 0x800 >; }; ... };

    The user can reduce this frequency by changing the above configuration, either manually or via the STM32CubeMX graphical user interface that allows generation of the corresponding device tree file.
    Notes:

    • The VDDcore voltage is specified in the regulators node of the board device tree, and it has to be kept consistent with the selected frequency, as explained in the overview above.
    • When the PLL1 static configuration is used, TF-A ignores the OPP table (see previous chapter) that may also be present in the device tree, so the secure monitor won't be able to answer to any upcoming frequency switch from Linux. It is therefore recommended to keep only one OPP in the table given to Linux, corresponding to the frequency setup by TF-A at boot time.

    4 Dynamic voltage and frequency scaling (DVFS) caution[edit]

    • As stated above, as soon as at least two operating points are defined in the OPP table, Linux kernel will automatically switch between them at runtime thanks to Linux cpufreq framework, configured with "ondemand" governor policy (see Documentation/admin-guide/pm/cpufreq.rst ). It is important to notice that cpufreq framework is only monitoring the CPU load to select the OPP because this can lead to some limitation during use cases where the CPU is not loaded a lot but high reactivity is needed to respect some real time constraints, like interrupt management. If you face some system issue where the CPU reactivity may be the root cause whereas DVFS is enabled, consider doing a trial with "performance" governor (see Documentation/admin-guide/pm/cpufreq.rst ).
    • Selecting OPP frequencies that can be reached with RCC MPUDIV dividor and without configuring again the PLL1 is recommended in order to get the fastest switch time between the OPP.


    {{ReviewsComments|-- [[User:Gerald Baeza|Gerald Baeza]] ([[User talk:Gerald Baeza|talk]]) 11:05, 4 November 2021 (CET)<br />To be updated for STM32MP13ApplicableFor
    |MPUs list=STM32MP13x, STM32MP15x
    |MPUs checklist=STM32MP13x, STM32MP15x}}
    ==Purpose==
    This article explains how to change the CPU '''operating point''' (also known as OPP). An operating point corresponds to the '''frequency''' of the processor and the  '''voltage''' that needs to be supplied to sustain it.<br>
    
    It also shows how it is possible to define multiple operating points, allowing the system to jump among them at run time: this is the '''dynamic voltage and frequency scaling (DVFS)'''. Some cautions are given at the end of the article, to help the user in its DVFS deployment.
    
    ==Hardware side==
    On {{MicroprocessorDevice | device=1}} products, the Cortex-A7 core is:
    * :
    * can be clocked by PLL1 from the [[RCC internal peripheral]]. The: the PLL1P output '''frequency''' can be directly propagated to the core, or it can go through an intermediate MPUDIV divider
    * is supplied with VDDcore '''voltage'''.
    The [[STM32MP15_microprocessor#Part_number_codification|part number]] tells which devices can be clocked 
    
    :* VDDCPU '''voltage''' on {{MicroprocessorDevice | device=13}}
    :* VDDCORE '''voltage''' on {{MicroprocessorDevice | device=15}}
    The '''part number''' tells the device maximum supported frequency, up to 1 GHz for the [[STM32MP13_microprocessor#Part_number_codification|STM32MP13]] or up to 800 MHz for the [[STM32MP15_microprocessor#Part_number_codification|STM32MP15]], with associated usage conditions. Otherwise, the frequency must be kept below 650 MHz.
    
    ==Software side==
    ===Overview===
    Two ways are offered to the user in order to set the CPU frequency:
    * By default, in OpenSTLinux distribution, the [[STM32 MPU device tree|"soc extension" device tree]] file defines an '''OPP table''' that contains one or several frequency / voltage pair(s)
    * Nevertheless, it is possible to directly define the expected '''PLL1 static configuration''' in the FSBL device tree
    
    {{Info | Whatever the implementation is, if your [[STM32MP15_microprocessor#Part_number_codification|part number]] supports up to 800 MHz, ensure that the VDDcore minimum '''voltage''' is increased from 1.2V to 1.35 V while running above 650 MHz}}
    
    ===OPP table===
    At boot time, TF-A automatically selects the '''fastest''' operating point that is suitable for the current [[STM32MP15 Boot time ===
    By default, in OpenSTLinux distribution, TF-A BL2 sets the CPU frequency to 650 MHz, that is the maximum frequency sustainable with the nominal voltage.<br><br>
    
    
    Notice that the processor must receive the nominal voltage during TF-A BL2 execution, whether configuring the STPMIC1 from TF-A BL2 itself or getting it from a discrete power supply, depending on the hardware board configuration.
    
    ==== On {{MicroprocessorDevice | device=13}} ====
    ===== VDDCPU voltage configuration =====
    The example below sets STPMIC1 BUCK1 minimal voltage to 1.25 V, allowing to provide the expected nominal voltage on VDDCPU for the CPU:<syntaxhighlight lang="c">
    
      vddcpu: buck1 {
        regulator-name = "vddcpu";
        regulator-min-microvolt = <1250000>;
        ...
    };</syntaxhighlight>
    
    
    ===== CPU frequency configuration =====
    TF-A recovers the CPU frequency configuration via the following [[Clock device tree configuration]] properties read:
    <syntaxhighlight lang="c">
    
    &rcc {
    	...
    	st,clksrc = <
    		CLK_MPU_PLL1P
    		...>;
    
    	st,pll_vco {
    		...
    		pll1_vco_1300Mhz: pll1-vco-1300Mhz {
    			src = < CLK_PLL12_HSE >;
    			divmn = < 2 80 >;
    			frac = < 0x800 >;
    		};
    	};
    	pll1:st,pll@0 {
    		...
    		st,pll = < &pll1_cfg1 >;
    		...
    		pll1_cfg1: pll1_cfg1 {
    			st,pll_vco = < &pll1_vco_1300Mhz >;
    			st,pll_div_pqr = < 0 1 1 >;
    		};
    	};</syntaxhighlight>
    
    
    ==== On {{MicroprocessorDevice | device=15}} ====
    ===== VDDCORE voltage configuration =====
    The example below sets STPMIC1 BUCK1 minimal voltage to 1.2 V, allowing to provide the expected nominal voltage on VDDCORE for the CPU:<syntaxhighlight lang="c">
    
      vddcore: buck1 {
        regulator-name = "vddcore";
        regulator-min-microvolt = <1200000>;
        ...
    };</syntaxhighlight>
    
    ===== CPU frequency configuration =====
    TF-A recovers the CPU frequency configuration via the following [[Clock device tree configuration]] properties read:<syntaxhighlight lang="c">
    
    &rcc {
    	...
    	/* VCO = 1300.0 MHz => P = 650 (CPU) */
    	pll1: st,pll@0 {
    		cfg = < 2 80 0 0 0 PQR(1,0,0) >;
    		frac = < 0x800 >;
    	};
    	...
    };</syntaxhighlight>
    
    
    === Runtime ===
    ==== On {{MicroprocessorDevice | device=13}} ====
    ===== Overview =====
    By default, in OpenSTLinux distribution, the OP-TEE [[STM32 MPU device tree|"soc extension" device tree]] file defines an '''OPP table''' that contains one or several frequency / voltage pair(s).
    
    {{Info | Whatever the implementation is, if your [[STM32MP13_microprocessor#Part_number_codification|part number]] according supports up to the OPP table ('''frequency''' and '''voltage''' couples) defined in the SOC extension device tree ({{CodeSource | TF-A | fdts/stm32mp15xa.dtsi}} or {{CodeSource | TF-A | fdts/stm32mp15xd.dtsi}}).<br>
    
    At runtime, the Linux will automatically 1 GHz, ensure that the VDDCPU minimum '''voltage''' is increased from 1.25 V to 1.35 V while running above 650 MHz}}
    
    ===== OPP table =====
    At runtime, Linux will automatically request to [[SCMI overview|OP-TEE SCMI]] interface to switch between the available operating points according to the CPU load and thanks to Linux cpufreq framework, configured with "ondemand" governor policy (see {{CodeSource | Linux kernel | Documentation/admin-guide/pm/cpufreq.rst}}). This feature is called dynamic voltage and frequency scaling (DVFS).<br>
    
    
    For instance, in the example below, two operating points ([800 MHz1 GHz ; 1.35 V]; [400650 MHz ; 1.225 V]) are defined for a 800 MHz1 GHz capable part number (opp-supported-hw = <0x2>), so TF-A will apply the [800 MHz ; 1.35 V] configuration at boot time and Linux will then dynamically jump between the two operating points ([800 MHz ; 1.35 V]; [400 MHz ; 1.2 V]) depending on the CPU load.<syntaxhighlight lang="c">
    
    &cpu0_opp_table {
    		opp-800000000 {
    			opp-hz = /bits/ 64 <800000000>;
    			opp-microvolt = <1350000>;
    			opp-supported-hw = <0x2>;
    		};
    		opp-400000000 {
    			opp-hz = /bits/ 64 <400000000>;
    			opp-microvolt = <1200000>;
    			opp-supported-hw = <0x2>;
    			opp-suspend;
    		};:<syntaxhighlight lang="c">
    
    &cpu0_opp_table {
    		opp-1000000000 {
    			opp-hz = /bits/ 64 <1000000000>;
    			opp-microvolt = <1350000>;
    			opp-supported-hw = <0x2>;
    			st,opp-default;
    		};
    
    		opp-650000000 {
    			opp-hz = /bits/ 64 <650000000>;
    			opp-microvolt = <1250000>;
    			opp-supported-hw = <0x2>;
    		};
    };</syntaxhighlight>
    
    The PLL1 configurations needed to reach the above frequencies must be described via the 'st,clk_opp' property in 'rcc' device tree node, like this is visible in {{CodeSource | OP-TEE_OS | core/arch/arm/dts/stm32mp135f-dk.dts}}:<syntaxhighlight lang="c">
    
    	st,clk_opp {
    		st,ck_mpu {
    			cfg_1 {
    				hz = < 1000000000 >;
    				st,clksrc = < CLK_MPU_PLL1P >;
    				st,pll = < &pll1_cfg2 >;
    			};
    			cfg_2 {
    				hz = < 650000000 >;
    				st,clksrc = < CLK_MPU_PLL1P >;
    				st,pll = < &pll1_cfg1 >;
    			};
    		};};</syntaxhighlight>
    
    Notes:
    * The operating point(s) supported by devices able to run above 650 MHz (and up to 800 MHz1 GHz) is/are identified by the '''opp-supported-hw''' property set to 0x2.
    * This same OPP table must be present in both the TF-A and Linux device tree
    * This description is valid for cold boot, but also when coming back from [[Power overview|Standby]] low power mode.* During cold boot, TF-A computes and saves the PLL1 settings for all operating points available in the device tree in compliance with the hardware capabilities. These saved paramaters are used later to increase the performance of the system-state transitions.
    
    ===PLL1 static configuration===
    The Cortex-A7 core frequency is selected at boot time, by the FSBL (TF-A), following the [[Clock device tree configuration - Bootloader specific]] syntax.<br>
    <syntaxhighlight lang="c">
    
    &rcc {
    	...
    	/* VCO = 1300.0 MHz => P = 650 (CPU) */
    	pll1: st,pll@0 {
    		cfg = < 2 80 0 0 0 PQR(1,0,0) >;
    		frac = < 0x800 >;
    	};
    	...
    };</syntaxhighlight>
    
    The user can reduce this frequency by changing the above configuration, either manually or via the  [[STM32CubeMX]] graphical user interface that allows generation of the corresponding device tree file.<br>
    
    Notes:
    * The VDDcore voltage is specified in the '''regulators''' node of the board device tree, and it has to be kept consistent with the selected frequency, as explained in the [[#Overview|overview]] above.
    * When the PLL1 static configuration is used, TF-A ignores the OPP table (see previous chapter) that may also be present in the device tree, so the secure monitor won't be able to answer to any upcoming frequency switch from Linux. It is therefore recommended to keep only one OPP in the table given to Linux, corresponding to the frequency setup by TF-A at boot time
    
    ==== On {{MicroprocessorDevice | device=15}} ====
    ===== Overview =====
    By default, in OpenSTLinux distribution, the Linux kernel [[STM32 MPU device tree|"soc extension" device tree]] file defines an '''OPP table''' that contains one or several frequency / voltage pair(s).
    {{Info | Whatever the implementation is, if your [[STM32MP15_microprocessor#Part_number_codification|part number]] supports up to 800 MHz, ensure that the VDDCORE minimum '''voltage''' is increased from 1.2 V to 1.35 V while running above 650 MHz}}
    
    ===== OPP table =====
    At runtime, the Linux kernel will automatically switch between the available operating points according to the CPU load and thanks to Linux cpufreq framework, configured with "ondemand" governor policy (see {{CodeSource | Linux kernel | Documentation/admin-guide/pm/cpufreq.rst}}). This feature is called dynamic voltage and frequency scaling (DVFS).<br>
    
    
    For instance, in the example below, two operating points ([800 MHz ; 1.35 V]; [400 MHz ; 1.2 V]) are defined for a 800 MHz capable part number (opp-supported-hw = <0x2>):<syntaxhighlight lang="c">
    
    &cpu0_opp_table {
    		opp-800000000 {
    			opp-hz = /bits/ 64 <800000000>;
    			opp-microvolt = <1350000>;
    			opp-supported-hw = <0x2>;
    		};
    		opp-400000000 {
    			opp-hz = /bits/ 64 <400000000>;
    			opp-microvolt = <1200000>;
    			opp-supported-hw = <0x2>;
    			opp-suspend;
    		};
    };</syntaxhighlight>
    
    Notes:
    * The operating point(s) supported by devices able to run above 650 MHz (and up to 800 MHz) is/are identified by the '''opp-supported-hw''' property set to 0x2.
    * This same OPP table must be present in both the BL32 (either OP-TEE or TF-A SP-MIN) and Linux device tree
    * This description is valid for cold boot, but also when coming back from [[Power overview|Standby]] low power mode.
    * During cold boot, BL32 (either OP-TEE or TF-A SP-MIN) computes and saves the PLL1 settings for all operating points available in the device tree in compliance with the hardware capabilities. These saved paramaters are used later to increase the performance of the system-state transitions.
    
    ==Dynamic voltage and frequency scaling (DVFS) caution==
    * As stated above, as soon as at least two operating points are defined in the OPP table, Linux kernel will automatically switch between them at runtime thanks to Linux cpufreq framework, configured with "ondemand" governor policy (see {{CodeSource | Linux kernel | Documentation/admin-guide/pm/cpufreq.rst}}). It is important to notice that cpufreq framework is only monitoring the CPU load to select the OPP because this can lead to some limitation during use cases where the CPU is not loaded a lot but high reactivity is needed to respect some real time constraints, like interrupt management. If you face some system issue where the CPU reactivity may be the root cause whereas DVFS is enabled, consider doing a trial with "performance" governor (see {{CodeSource | Linux kernel | Documentation/admin-guide/pm/cpufreq.rst}}).
    * Selecting OPP frequencies that can be reached with [[RCC internal peripheral|RCC]] MPUDIV dividor and without configuring again the PLL1 is recommended in order to get the fastest switch time between the OPP. <noinclude>
    
    [[Category:How to customize software]]
    {{PublicationRequestId | 14900 | 2020-02-11 | AnneJ}}</noinclude>
    (38 intermediate revisions by 3 users not shown)
    Line 1: Line 1:
    {{ReviewsComments|-- [[User:Gerald Baeza|Gerald Baeza]] ([[User talk:Gerald Baeza|talk]]) 11:05, 4 November 2021 (CET)<br />To be updated for STM32MP13}}
    +
    {{ApplicableFor
      +
    |MPUs list=STM32MP13x, STM32MP15x
      +
    |MPUs checklist=STM32MP13x, STM32MP15x
      +
    }}
     
    ==Purpose==
     
    ==Purpose==
     
    This article explains how to change the CPU '''operating point''' (also known as OPP). An operating point corresponds to the '''frequency''' of the processor and the  '''voltage''' that needs to be supplied to sustain it.<br>
     
    This article explains how to change the CPU '''operating point''' (also known as OPP). An operating point corresponds to the '''frequency''' of the processor and the  '''voltage''' that needs to be supplied to sustain it.<br>
    Line 5: Line 8:
       
     
    ==Hardware side==
     
    ==Hardware side==
    On {{MicroprocessorDevice | device=1}} products, the Cortex-A7 core is:
    +
    On {{MicroprocessorDevice | device=1}} products, the Cortex-A7 core:
    * clocked by PLL1 from the [[RCC internal peripheral]]. The PLL1P output '''frequency''' can be directly propagated to the core, or it can go through an intermediate MPUDIV divider
    +
    * can be clocked by PLL1 from the [[RCC internal peripheral]]: the PLL1P output '''frequency''' can be directly propagated to the core, or it can go through an intermediate MPUDIV divider
    * supplied with VDDcore '''voltage'''.
    +
    * is supplied with  
    The [[STM32MP15_microprocessor#Part_number_codification|part number]] tells which devices can be clocked up to 800 MHz, with associated usage conditions. Otherwise, the frequency must be kept below 650 MHz.
    +
    :* VDDCPU '''voltage''' on {{MicroprocessorDevice | device=13}}
      +
    :* VDDCORE '''voltage''' on {{MicroprocessorDevice | device=15}}
      +
    The '''part number''' tells the device maximum supported frequency, up to 1 GHz for the [[STM32MP13_microprocessor#Part_number_codification|STM32MP13]] or up to 800 MHz for the [[STM32MP15_microprocessor#Part_number_codification|STM32MP15]], with associated usage conditions. Otherwise, the frequency must be kept below 650 MHz.
       
     
    ==Software side==
     
    ==Software side==
    ===Overview===
    +
    === Boot time ===
    Two ways are offered to the user in order to set the CPU frequency:
    +
    By default, in OpenSTLinux distribution, TF-A BL2 sets the CPU frequency to 650 MHz, that is the maximum frequency sustainable with the nominal voltage.<br><br>
    * By default, in OpenSTLinux distribution, the [[STM32 MPU device tree|"soc extension" device tree]] file defines an '''OPP table''' that contains one or several frequency / voltage pair(s)
     
    * Nevertheless, it is possible to directly define the expected '''PLL1 static configuration''' in the FSBL device tree
     
       
    {{Info | Whatever the implementation is, if your [[STM32MP15_microprocessor#Part_number_codification|part number]] supports up to 800 MHz, ensure that the VDDcore minimum '''voltage''' is increased from 1.2V to 1.35 V while running above 650 MHz}}
    +
    Notice that the processor must receive the nominal voltage during TF-A BL2 execution, whether configuring the STPMIC1 from TF-A BL2 itself or getting it from a discrete power supply, depending on the hardware board configuration.
       
    ===OPP table===
    +
    ==== On {{MicroprocessorDevice | device=13}} ====
    At boot time, TF-A automatically selects the '''fastest''' operating point that is suitable for the current [[STM32MP15_microprocessor#Part_number_codification|part number]] according to the OPP table ('''frequency''' and '''voltage''' couples) defined in the SOC extension device tree ({{CodeSource | TF-A | fdts/stm32mp15xa.dtsi}} or {{CodeSource | TF-A | fdts/stm32mp15xd.dtsi}}).<br>
    +
    ===== VDDCPU voltage configuration =====
    At runtime, the Linux will automatically switch between the available operating points according to the CPU load and thanks to Linux cpufreq framework, configured with "ondemand" governor policy (see {{CodeSource | Linux kernel | Documentation/admin-guide/pm/cpufreq.rst}}). This feature is called dynamic voltage and frequency scaling (DVFS).<br>
    +
    The example below sets STPMIC1 BUCK1 minimal voltage to 1.25 V, allowing to provide the expected nominal voltage on VDDCPU for the CPU:
      +
    <syntaxhighlight lang="c">
      +
      vddcpu: buck1 {
      +
        regulator-name = "vddcpu";
      +
        regulator-min-microvolt = <1250000>;
      +
        ...
      +
    };
      +
    </syntaxhighlight>
      +
     
      +
    ===== CPU frequency configuration =====
      +
    TF-A recovers the CPU frequency configuration via the following [[Clock device tree configuration]] properties read:
      +
     
      +
    <syntaxhighlight lang="c">
      +
    &rcc {
      +
    ...
      +
    st,clksrc = <
      +
    CLK_MPU_PLL1P
      +
    ... >;
      +
     
      +
    st,pll_vco {
      +
    ...
      +
    pll1_vco_1300Mhz: pll1-vco-1300Mhz {
      +
    src = < CLK_PLL12_HSE >;
      +
    divmn = < 2 80 >;
      +
    frac = < 0x800 >;
      +
    };
      +
    };
      +
    pll1:st,pll@0 {
      +
    ...
      +
    st,pll = < &pll1_cfg1 >;
      +
    ...
      +
    pll1_cfg1: pll1_cfg1 {
      +
    st,pll_vco = < &pll1_vco_1300Mhz >;
      +
    st,pll_div_pqr = < 0 1 1 >;
      +
    };
      +
    };
      +
    </syntaxhighlight>
      +
     
      +
    ==== On {{MicroprocessorDevice | device=15}} ====
      +
    ===== VDDCORE voltage configuration =====
      +
    The example below sets STPMIC1 BUCK1 minimal voltage to 1.2 V, allowing to provide the expected nominal voltage on VDDCORE for the CPU:
      +
    <syntaxhighlight lang="c">
      +
      vddcore: buck1 {
      +
        regulator-name = "vddcore";
      +
        regulator-min-microvolt = <1200000>;
      +
        ...
      +
    };
      +
    </syntaxhighlight>
      +
    ===== CPU frequency configuration =====
      +
    TF-A recovers the CPU frequency configuration via the following [[Clock device tree configuration]] properties read:
      +
    <syntaxhighlight lang="c">
      +
    &rcc {
      +
    ...
      +
    /* VCO = 1300.0 MHz => P = 650 (CPU) */
      +
    pll1: st,pll@0 {
      +
    cfg = < 2 80 0 0 0 PQR(1,0,0) >;
      +
    frac = < 0x800 >;
      +
    };
      +
    ...
      +
    };
      +
    </syntaxhighlight>
      +
     
      +
    === Runtime ===
      +
    ==== On {{MicroprocessorDevice | device=13}} ====
      +
    ===== Overview =====
      +
    By default, in OpenSTLinux distribution, the OP-TEE [[STM32 MPU device tree|"soc extension" device tree]] file defines an '''OPP table''' that contains one or several frequency / voltage pair(s).
      +
     
      +
    {{Info | Whatever the implementation is, if your [[STM32MP13_microprocessor#Part_number_codification|part number]] supports up to 1 GHz, ensure that the VDDCPU minimum '''voltage''' is increased from 1.25 V to 1.35 V while running above 650 MHz}}
      +
     
      +
    ===== OPP table =====
      +
    At runtime, Linux will automatically request to [[SCMI overview|OP-TEE SCMI]] interface to switch between the available operating points according to the CPU load and thanks to Linux cpufreq framework, configured with "ondemand" governor policy (see {{CodeSource | Linux kernel | Documentation/admin-guide/pm/cpufreq.rst}}). This feature is called dynamic voltage and frequency scaling (DVFS).<br>
      +
     
      +
    For instance, in the example below, two operating points ([1 GHz ; 1.35 V]; [650 MHz ; 1.25 V]) are defined for a 1 GHz capable part number (opp-supported-hw = <0x2>):
      +
    <syntaxhighlight lang="c">
      +
    &cpu0_opp_table {
      +
    opp-1000000000 {
      +
    opp-hz = /bits/ 64 <1000000000>;
      +
    opp-microvolt = <1350000>;
      +
    opp-supported-hw = <0x2>;
      +
    st,opp-default;
      +
    };
      +
     
      +
    opp-650000000 {
      +
    opp-hz = /bits/ 64 <650000000>;
      +
    opp-microvolt = <1250000>;
      +
    opp-supported-hw = <0x2>;
      +
    };
      +
    };
      +
    </syntaxhighlight>
      +
    The PLL1 configurations needed to reach the above frequencies must be described via the 'st,clk_opp' property in 'rcc' device tree node, like this is visible in {{CodeSource | OP-TEE_OS | core/arch/arm/dts/stm32mp135f-dk.dts}}:
      +
    <syntaxhighlight lang="c">
      +
    st,clk_opp {
      +
    st,ck_mpu {
      +
    cfg_1 {
      +
    hz = < 1000000000 >;
      +
    st,clksrc = < CLK_MPU_PLL1P >;
      +
    st,pll = < &pll1_cfg2 >;
      +
    };
      +
    cfg_2 {
      +
    hz = < 650000000 >;
      +
    st,clksrc = < CLK_MPU_PLL1P >;
      +
    st,pll = < &pll1_cfg1 >;
      +
    };
      +
    };
      +
    };
      +
    </syntaxhighlight>
      +
    Notes:
      +
    * The operating point(s) supported by devices able to run above 650 MHz (and up to 1 GHz) is/are identified by the '''opp-supported-hw''' property set to 0x2.
      +
    * This description is valid for cold boot, but also when coming back from [[Power overview|Standby]] low power mode.
      +
     
      +
    ==== On {{MicroprocessorDevice | device=15}} ====
      +
    ===== Overview =====
      +
    By default, in OpenSTLinux distribution, the Linux kernel [[STM32 MPU device tree|"soc extension" device tree]] file defines an '''OPP table''' that contains one or several frequency / voltage pair(s).
      +
    {{Info | Whatever the implementation is, if your [[STM32MP15_microprocessor#Part_number_codification|part number]] supports up to 800 MHz, ensure that the VDDCORE minimum '''voltage''' is increased from 1.2 V to 1.35 V while running above 650 MHz}}
      +
     
      +
    ===== OPP table =====
      +
    At runtime, the Linux kernel will automatically switch between the available operating points according to the CPU load and thanks to Linux cpufreq framework, configured with "ondemand" governor policy (see {{CodeSource | Linux kernel | Documentation/admin-guide/pm/cpufreq.rst}}). This feature is called dynamic voltage and frequency scaling (DVFS).<br>
       
    For instance, in the example below, two operating points ([800 MHz ; 1.35 V]; [400 MHz ; 1.2 V]) are defined for a 800 MHz capable part number (opp-supported-hw = <0x2>), so TF-A will apply the [800 MHz ; 1.35 V] configuration at boot time and Linux will then dynamically jump between the two operating points ([800 MHz ; 1.35 V]; [400 MHz ; 1.2 V]) depending on the CPU load.
    +
    For instance, in the example below, two operating points ([800 MHz ; 1.35 V]; [400 MHz ; 1.2 V]) are defined for a 800 MHz capable part number (opp-supported-hw = <0x2>):
     
    <syntaxhighlight lang="c">
     
    <syntaxhighlight lang="c">
     
    &cpu0_opp_table {
     
    &cpu0_opp_table {
    Line 40: Line 159:
     
    Notes:
     
    Notes:
     
    * The operating point(s) supported by devices able to run above 650 MHz (and up to 800 MHz) is/are identified by the '''opp-supported-hw''' property set to 0x2.
     
    * The operating point(s) supported by devices able to run above 650 MHz (and up to 800 MHz) is/are identified by the '''opp-supported-hw''' property set to 0x2.
    * This same OPP table must be present in both the TF-A and Linux device tree
    +
    * This same OPP table must be present in both the BL32 (either OP-TEE or TF-A SP-MIN) and Linux device tree
     
    * This description is valid for cold boot, but also when coming back from [[Power overview|Standby]] low power mode.
     
    * This description is valid for cold boot, but also when coming back from [[Power overview|Standby]] low power mode.
    * During cold boot, TF-A computes and saves the PLL1 settings for all operating points available in the device tree in compliance with the hardware capabilities. These saved paramaters are used later to increase the performance of the system-state transitions.
    +
    * During cold boot, BL32 (either OP-TEE or TF-A SP-MIN) computes and saves the PLL1 settings for all operating points available in the device tree in compliance with the hardware capabilities. These saved paramaters are used later to increase the performance of the system-state transitions.
     
     
    ===PLL1 static configuration===
     
    The Cortex-A7 core frequency is selected at boot time, by the FSBL (TF-A), following the [[Clock device tree configuration - Bootloader specific]] syntax.<br>
     
    <syntaxhighlight lang="c">
     
    &rcc {
     
    ...
     
    /* VCO = 1300.0 MHz => P = 650 (CPU) */
     
    pll1: st,pll@0 {
     
    cfg = < 2 80 0 0 0 PQR(1,0,0) >;
     
    frac = < 0x800 >;
     
    };
     
    ...
     
    };
     
    </syntaxhighlight>
     
    The user can reduce this frequency by changing the above configuration, either manually or via the  [[STM32CubeMX]] graphical user interface that allows generation of the corresponding device tree file.
     
    <br>
     
    Notes:
     
    * The VDDcore voltage is specified in the '''regulators''' node of the board device tree, and it has to be kept consistent with the selected frequency, as explained in the [[#Overview|overview]] above.
     
    * When the PLL1 static configuration is used, TF-A ignores the OPP table (see previous chapter) that may also be present in the device tree, so the secure monitor won't be able to answer to any upcoming frequency switch from Linux. It is therefore recommended to keep only one OPP in the table given to Linux, corresponding to the frequency setup by TF-A at boot time.
     
       
     
    ==Dynamic voltage and frequency scaling (DVFS) caution==
     
    ==Dynamic voltage and frequency scaling (DVFS) caution==