Difference between revisions of "How to bring-up a custom board : procedure"

[quality revision] [pending revision]
m (Replaced content with "<noinclude> Category:How to design products with STM32 MPU </noinclude> {{UnderConstruction}} ==Purpose== The new design board is received and you wonders how to ge...")
(Tag: Replaced)
m (Load & launch TF-A)
 


Under construction.png

Contents

Coming soon

1 Purpose[edit]

The new design board is received and you wonders wonder how to get started with the new chip set composed of STMP32MP1x, DDR RAM , STPMIC for power supply. What tool to use ? What care to be taken to configure the boot chain your application ? What to check if the boot chains fails ? chain fails ?

2 Procedure[edit]

Describes what has to be configured or checked to load for the first time

  • TF-A in SYSRAM by ROMCode ,
  • initializes the DDR and
  • Load and starts Uboot in DDR.

TF-A and Uboot firmware are picked-up by ROMCode from UBOOT serial link or from Sdcard.

A troubleshooting grid for classical pitfalls is visible in Bring-up troubleshooting grid

2.1 Check TF-A configuration against PCB[edit]

Configuration is done in the device tree files of TF-A

Two possibilities :

  1. your PCB is same as ST reference board for the HSE/UART/IC2 for PMIC/DRAM/SDMMC subsytems : you can reuse the TF-A device tree files provided with OpenSTLinux delivery for the board.
  2. your PCB is different from ST reference board, you can adapt in the ST reference board device tree file: the pin-out, the clock configuration of UART (for traces), I2Cx for STPMIC control and HSE source configuration .

Please find further information in §2.1 in how to create your board device

Please find further information about device tree HSE pin configuration §3.1.1.2 in clock device tree configuration (bootloader specific)

Please find further information about STPMIC1x I2Cx configuration in §3 in how to create your board device

Warning.png The device tree files generated by STM32CubeMx is incomplete, it cannot be used as it

CubeMX handles only the Pin muxing , the DDR settings, the RCC settings and HW execution context for peripheral isolation. The parameters of each peripheral node in the device tree files have to be added manually. See the articles of the peripherals - hardware blocks category that describe for each peripheral the device tree parameters. If needed, the I2C4 STPMIC node and "Pwr", have to be picked from the TF-A device tree of the ST reference boards.

2.2 Load & launch TF-A[edit]

Two alternatives :

  • Start TF-A with CubeProg in UART or USB OTG

1/ boot TF-A with serial link with UART (simplest solution UART different from TF-A trace UART, UART4 by default) or if your design has USB-OTG (2 dedicated pins for USB-OTG in DS) from USB-OTG with CubeProgrammer.

In .tsv file put only the first lines of the eval trusted boot chain, CubeProgammer and RomCode will load TF-A in internal SYSRAM and start its execution.

You should see the TF-A traces on the UART (uart4 is by default in DT of TF-A).

  • Start TF-A from SDCard (If your design has a SDCard) .

You can go faster by booting the SDCard with your TF-A and Uboot inside.

In case TF-A does not start (no traces in Uart4 or PA13 RomCode debug pin state) because there is an issue on SDCard PCB, the CubeProgrammer over UART (not UART4 as used already by TF-A) is the fallback approach.


Once you will have been able to load and execute successful TF-A you should see

"Warning: DDR not configured"

2.3 Configuration of the DDR[edit]

2.3.1 DDR parameters in Device Tree[edit]

DDR timings are loaded in DDR controller registers by FSBL and the register values are located in the FSBL device tree files ( *.dtsi) files of TF-A binary (or Uboot-SPL for basic boot chain) .

To build these files, there are 2 possibilities:

  1. your PCB contains a DDR3L@533Mhz you can re-use directly the ST reference boards (select the stm32mp15-ddr3-2x4Gb-1066-binG.dtsi or stm32mp15-ddr3-1x4Gb-1066-binG.dtsi according to your configuration). The timings can be applied for any DDR3L with the DDR Speed/bin Grade 1066-G .
  2. your PCB uses another configuration, the STM32CubeMx / DDR Tool will help you to compute the DDR timing configuration and will generate the device tree file relative to DDR settings.

2.3.2 Recompile TF-A with ddr dtsi files[edit]

You should see the TF-A trace (dk2 example on V1.0.0)

"INFO: RAM: DDR3-1066/888 bin G 1x4Gb 533MHz v1.41

INFO: Memory size = 0x20000000 (512 MB) ……

SP_MIN: Preparing exit to normal world "

then you should be able to load&launch Uboot in DDR


2.3.3 DDR timing fine-tuning and test[edit]

Two possibities:

  • DDR works (no strange behavior with Uboot) at this stage, skip the DDR tool tests/finetuning step.

For the bring up you can use loose DDR timings configuration.

Later for product phase to support all the temperatures, the product longevity, DDR tool should be used to run the fine-tuned Data line byte delays.


  • DDR does not works fine

1 check the pin muxing of the DDR signals against PCB schemtatics

2 check the voltages VDD-DDR, VREF_DDR, VDD-VTT on the PCB (also in DT of UbootSPL PMIC node)

3 check DDR timing (for DDR3 Speed bin / grade) against data sheet of DRAM


How to run DDR tests and fine-tune the DDR timings with the CubeMX DDR tool tab ?

Adjust to PCB the UbootSPL Device Tree files (HSE,Uart trace,PMIC pin&Voltage) -should have the same TF-A nodes for these perif. Recompile UbootSPL (in Uboot folder, device tree files are shared between Uboot and UbootSPL). Run tuning with CubeMx DDR tool tab. Behind CubeMx, CubeProgrammer feeds UART4 when bootrom boots on UART4 and loads & launches in SYRAM UbootSPL in DDR interactive mode. CubeMx DDR tool can then control DDR tuning & tests.

-Boot pin are set on serial. "Connect" (in CubeMX DDR tool tab) via UART4 (or VCP with ST-link) to UbootSPL.

-Launch DDR tuning and tests DDR

-Save DDR parameters in Device tree DDR file.

Recompile TF-A with the generated DT DDR file to get TF-A with the finetuned parameters. Fine tune parameters are the over all the products (Depends on design not manufacturing).


2.4 Check Uboot configuration[edit]

2.4.1 Check the bottom DDR address according to the DDR size[edit]

The botton address is define in Uboot DT

Ex for eval (8GBits) :

memory@c0000000 {
    reg = <0xc0000000 0x40000000>;
};

From a CubeMx Uboot dts file

Add:

-Same powers nodes as TF-A, according to the design (if STMPIC is on the design (I2C4 with PMIC node & pwr/pwr-regulators (for internal regulator supplies). In descrete no need to add these 2 nodes).

-same admmc1 node as TF-A, according to the SDMMC design (with or without levelshifter see pitfall)

2.5 Load Uboot in DDR[edit]

Similar methods to TF-A boot: from serial link with cubeprogrammer or from Sdcard (if available)

In .tsv , 2 first lines with binaries of TF-A (Id=0x1) and Uboot (id=0x3).

2.6 Kernel bring-up[edit]

Start from a dts file where all the peripheral nodes are disabled.

For each of them you have the device tree a first description in the wiki to add the adapted properties according to your PCB in the peripheral nodes.

Entry for the device tree description: article in the device tree configuration category

(You can also use the ST boards device tree files and relative schematics as example).

3 Back ground knowledge[edit]

3.1 Reset signal on PowerOn sequence with ROM Code and PMIC[edit]

When you power ON the STPMIC, it enters in internal POWER_UP state, NRST goes to 0 , when VDD and VDDCore are set and at the right level STPMIC goes from POWER_UP to internal POWER-START state and releases NRST but is maintained to 0 by MP1. The MP1 PowerOn Reset (POR) has detected the right level of VDD and VDDCORE and some delay elapsed the MP1 releases NRST, then ROM code is started. (NSRET PAD is open drain with internal pull-up) . PWR_ON goes to 1 once VDD is > POR/BOR threshold . PWR_ON should be 1 .

RM reference : 9.3.2 PWR supply system startup sequence

10.3.14 Power-on and wakeup sequences

<noinclude>

[[Category:How to design products with STM32 MPU]]</noinclude>

{{UnderConstruction}}
==Purpose==

The new design board is received and you wonderswonder how to get started with the new chip set composed of  STMP32MP1x, DDR RAM , STPMIC for power supply.
What tool to use ? 
What care to be taken to configure the boot chain your application ?
What to check if the boot chainschain fails ?


==Procedure==

Describes what has to be configured or checked to load for the first time

* TF-A in SYSRAM by ROMCode ,
* initializes the DDR and
* Load and starts Uboot in DDR.

TF-A and Uboot firmware are picked-up by ROMCode from UBOOT serial link or from Sdcard.

A troubleshooting grid for classical pitfalls is visible in '''[[Bring-up troubleshooting grid|Bring-up troubleshooting grid]]'''

=== Check TF-A configuration against PCB === 

Configuration is done in the device tree files of TF-A

Two possibilities :

# ''your PCB is same as ST reference board'' for the HSE/UART/IC2 for PMIC/DRAM/SDMMC subsytems : you can reuse the TF-A device tree files provided with OpenSTLinux delivery for the board.
# ''your PCB is different from ST reference board'', you can adapt in the ST reference board device tree file: the pin-out, the clock configuration of UART (for traces), I2Cx  for STPMIC control and HSE source configuration .

Please find further information in §2.1 in [[How_to_create_your_board_device_tree|how to create your board device]]

Please find further information about device tree HSE pin configuration §3.1.1.2 in [[Clock_device_tree_configuration_-_Bootloader_specific|clock device tree configuration (bootloader specific)]]

Please find further information about STPMIC1x I2Cx configuration in §3 in [[How_to_create_your_board_device_tree|how to create your board device]]

{{Warning | The device tree files generated by STM32CubeMx is incomplete, it cannot be used as it}}

CubeMX handles only the Pin muxing , the DDR settings, the RCC settings and HW execution context for peripheral isolation. The parameters of each peripheral node in the device tree files have to be added manually. See the articles of the [[:Category:Peripherals_-_Hardware_blocks|peripherals - hardware blocks]] category that describe for each peripheral the device tree parameters. If needed, the I2C4 STPMIC node and "Pwr", have to be picked from the TF-A device tree of the ST reference boards.

=== Load & launch TF-A ===
Two alternatives :

* Start TF-A with CubeProg in UART or USB OTG
1/ boot TF-A with serial link with UART (simplest solution UART different from TF-A trace UART, UART4 by default) or if your design has USB-OTG (2 dedicated pins for USB-OTG in DS) from USB-OTG with CubeProgrammer.

In .tsv file put only the first lines of the eval trusted boot chain, CubeProgammer and RomCode will load TF-A in internal SYSRAM and start its execution.

You should see the TF-A traces on the UART (uart4 is by default in DT of TF-A).

* Start TF-A from SDCard (If your design has a SDCard) .
You can go faster by booting the SDCard with your TF-A and Uboot inside.

In case TF-A does not start (no traces in Uart4 or PA13 RomCode debug pin state) because there is an issue on SDCard PCB,  the CubeProgrammer over UART (not UART4 as used already by TF-A) is the fallback approach.

Once you will have been able to load and execute successful TF-A you should see

 "Warning: DDR not configured"

=== Configuration of the DDR ===

==== DDR parameters in Device Tree ====

DDR timings are loaded in DDR controller registers by FSBL and the register values are located in the FSBL device tree files ( *.dtsi) files of TF-A binary (or Uboot-SPL for basic boot chain) .

To build these files, there are 2 possibilities:

#your PCB contains a DDR3L@533Mhz you can re-use directly the ST reference boards (select the stm32mp15-ddr3-2x4Gb-1066-binG.dtsi or stm32mp15-ddr3-1x4Gb-1066-binG.dtsi according to your configuration). The timings can be applied for any DDR3L with the DDR Speed/bin Grade 1066-G .
#your PCB uses another configuration, the STM32CubeMx / DDR Tool will help you to compute the DDR timing configuration and will generate the device tree file relative to DDR settings.

==== Recompile TF-A with ddr dtsi files ====

You should see the TF-A trace (dk2 example on V1.0.0)   

"INFO:    RAM: DDR3-1066/888 bin G 1x4Gb 533MHz v1.41                           

INFO:    Memory size = 0x20000000 (512 MB)  ……

SP_MIN: Preparing exit to normal world  "

 then you should be able to load&launch Uboot in DDR


==== DDR timing fine-tuning and test ====

Two possibities:

* DDR works (no strange behavior with Uboot) at this stage, skip the DDR tool tests/finetuning step.
For the bring up you can use loose DDR timings configuration.

Later for product phase to support all the temperatures, the product longevity, DDR tool should be used to run the fine-tuned Data line byte delays. 


* DDR does not works fine

1 check the pin muxing of the DDR signals against PCB schemtatics

2 check the voltages VDD-DDR, VREF_DDR, VDD-VTT on the PCB (also in DT of UbootSPL PMIC node)

3 check DDR timing (for DDR3 Speed bin / grade) against data sheet of DRAM

How to run DDR tests and fine-tune the DDR timings with the CubeMX DDR tool tab ?

Adjust to PCB the UbootSPL Device Tree files (HSE,Uart trace,PMIC pin&Voltage) -should have the same TF-A nodes for these perif. Recompile UbootSPL (in Uboot folder, device tree files are shared between Uboot and UbootSPL).   
Run tuning with CubeMx DDR tool tab.
Behind CubeMx, CubeProgrammer feeds UART4 when bootrom boots on UART4 and loads & launches in SYRAM UbootSPL in DDR interactive mode. CubeMx DDR tool can then control DDR tuning & tests.

-Boot pin are set on serial.  "Connect" (in CubeMX DDR tool tab) via UART4 (or VCP with ST-link) to UbootSPL.

-Launch DDR tuning and tests DDR

-Save DDR parameters in Device tree DDR file.

Recompile TF-A with the generated DT DDR file to get TF-A with the finetuned parameters. Fine tune parameters are the over all the products (Depends on design not manufacturing).

=== Check Uboot configuration === 

==== Check the bottom DDR address according to the DDR size ====

The botton address is define in Uboot DT

Ex for eval (8GBits) :

 memory@c0000000 {
     reg = <0xc0000000 0x40000000>;
 };

From a CubeMx Uboot dts file

Add:

-Same powers nodes as TF-A, according to the design (if STMPIC is on the design (I2C4 with PMIC node & pwr/pwr-regulators (for internal regulator supplies). In descrete no need to add these 2 nodes).

-same admmc1 node as TF-A, according to the SDMMC design (with or without levelshifter see pitfall)

=== Load Uboot in DDR ===

Similar methods to TF-A boot: from serial link with cubeprogrammer or from Sdcard (if available)

In .tsv , 2 first lines with binaries of TF-A (Id=0x1) and Uboot (id=0x3).

=== Kernel bring-up ===

Start from a dts file where all the peripheral nodes are disabled.

For each of them you have the device tree a first description in the wiki to add the adapted properties according to your PCB in the peripheral nodes.

Entry for the device tree description: article in the [[:Category:Device_tree_configuration|device tree configuration]] category

(You can also use the ST boards device tree files and relative schematics as example).

== Back ground knowledge ==

=== Reset signal on PowerOn sequence with ROM Code and PMIC === 
When you power ON the STPMIC, it enters in internal POWER_UP state, NRST goes to 0 , when VDD and VDDCore are set and at the right level STPMIC goes from POWER_UP to internal POWER-START state and releases NRST but is maintained to 0 by MP1. The MP1 PowerOn Reset (POR) has detected the right level of VDD and VDDCORE and some delay elapsed the MP1 releases NRST, then ROM code is started. (NSRET PAD is open drain with internal pull-up) . PWR_ON goes to 1 once VDD is > POR/BOR threshold . PWR_ON should be 1 . 

RM reference :      9.3.2 PWR supply system startup sequence

10.3.14 Power-on and wakeup sequences
(5 intermediate revisions by 2 users not shown)
Line 2: Line 2:
 
[[Category:How to design products with STM32 MPU]]
 
[[Category:How to design products with STM32 MPU]]
 
</noinclude>
 
</noinclude>
 
{{UnderConstruction}}
 
   
 
==Purpose==
 
==Purpose==
   
The new design board is received and you wonders how to get started with the new chip set composed of  STMP32MP1x, DDR RAM , STPMIC for power supply.
+
The new design board is received and you wonder how to get started with the new chip set composed of  STMP32MP1x, DDR RAM , STPMIC for power supply.
 
What tool to use ?  
 
What tool to use ?  
 
What care to be taken to configure the boot chain your application ?
 
What care to be taken to configure the boot chain your application ?
What to check if the boot chains fails ?
+
What to check if the boot chain fails ?
  +
 
  +
==Procedure==
  +
 
  +
Describes what has to be configured or checked to load for the first time
  +
 
  +
* TF-A in SYSRAM by ROMCode ,
  +
* initializes the DDR and
  +
* Load and starts Uboot in DDR.
  +
 
  +
TF-A and Uboot firmware are picked-up by ROMCode from UBOOT serial link or from Sdcard.
  +
 
  +
A troubleshooting grid for classical pitfalls is visible in '''[[Bring-up troubleshooting grid|Bring-up troubleshooting grid]]'''
  +
 
  +
=== Check TF-A configuration against PCB ===
  +
 
  +
Configuration is done in the device tree files of TF-A
  +
 
  +
Two possibilities :
  +
 
  +
# ''your PCB is same as ST reference board'' for the HSE/UART/IC2 for PMIC/DRAM/SDMMC subsytems : you can reuse the TF-A device tree files provided with OpenSTLinux delivery for the board.
  +
# ''your PCB is different from ST reference board'', you can adapt in the ST reference board device tree file: the pin-out, the clock configuration of UART (for traces), I2Cx  for STPMIC control and HSE source configuration .
  +
 
  +
Please find further information in §2.1 in [[How_to_create_your_board_device_tree|how to create your board device]]
  +
  +
Please find further information about device tree HSE pin configuration §3.1.1.2 in [[Clock_device_tree_configuration_-_Bootloader_specific|clock device tree configuration (bootloader specific)]]
  +
 
  +
Please find further information about STPMIC1x I2Cx configuration in §3 in [[How_to_create_your_board_device_tree|how to create your board device]]
  +
 
  +
{{Warning | The device tree files generated by STM32CubeMx is incomplete, it cannot be used as it}}
  +
 
  +
CubeMX handles only the Pin muxing , the DDR settings, the RCC settings and HW execution context for peripheral isolation. The parameters of each peripheral node in the device tree files have to be added manually. See the articles of the [[:Category:Peripherals_-_Hardware_blocks|peripherals - hardware blocks]] category that describe for each peripheral the device tree parameters. If needed, the I2C4 STPMIC node and "Pwr", have to be picked from the TF-A device tree of the ST reference boards.
  +
 
  +
=== Load & launch TF-A ===
  +
Two alternatives :
  +
 
  +
* Start TF-A with CubeProg in UART or USB OTG
  +
1/ boot TF-A with serial link with UART (simplest solution UART different from TF-A trace UART, UART4 by default) or if your design has USB-OTG (2 dedicated pins for USB-OTG in DS) from USB-OTG with CubeProgrammer.
  +
 
  +
In .tsv file put only the first lines of the eval trusted boot chain, CubeProgammer and RomCode will load TF-A in internal SYSRAM and start its execution.
  +
 
  +
You should see the TF-A traces on the UART (uart4 is by default in DT of TF-A).
  +
 
  +
* Start TF-A from SDCard (If your design has a SDCard) .
  +
You can go faster by booting the SDCard with your TF-A and Uboot inside.
  +
 
  +
In case TF-A does not start (no traces in Uart4 or PA13 RomCode debug pin state) because there is an issue on SDCard PCB,  the CubeProgrammer over UART (not UART4 as used already by TF-A) is the fallback approach.
  +
 
  +
  +
Once you will have been able to load and execute successful TF-A you should see
  +
 
  +
"Warning: DDR not configured"
  +
 
  +
=== Configuration of the DDR ===
  +
 
  +
==== DDR parameters in Device Tree ====
  +
 
  +
DDR timings are loaded in DDR controller registers by FSBL and the register values are located in the FSBL device tree files ( *.dtsi) files of TF-A binary (or Uboot-SPL for basic boot chain) .
  +
 
  +
To build these files, there are 2 possibilities:
  +
 
  +
#your PCB contains a DDR3L@533Mhz you can re-use directly the ST reference boards (select the stm32mp15-ddr3-2x4Gb-1066-binG.dtsi or stm32mp15-ddr3-1x4Gb-1066-binG.dtsi according to your configuration). The timings can be applied for any DDR3L with the DDR Speed/bin Grade 1066-G .
  +
#your PCB uses another configuration, the STM32CubeMx / DDR Tool will help you to compute the DDR timing configuration and will generate the device tree file relative to DDR settings.
  +
 
  +
==== Recompile TF-A with ddr dtsi files ====
  +
 
  +
You should see the TF-A trace (dk2 example on V1.0.0) 
  +
 
  +
"INFO:    RAM: DDR3-1066/888 bin G 1x4Gb 533MHz v1.41                         
  +
 
  +
INFO:    Memory size = 0x20000000 (512 MB)  ……
  +
 
  +
SP_MIN: Preparing exit to normal world  "
  +
 
  +
then you should be able to load&launch Uboot in DDR
  +
 
  +
  +
 
  +
==== DDR timing fine-tuning and test ====
  +
 
  +
Two possibities:
  +
 
  +
* DDR works (no strange behavior with Uboot) at this stage, skip the DDR tool tests/finetuning step.
  +
For the bring up you can use loose DDR timings configuration.
  +
 
  +
Later for product phase to support all the temperatures, the product longevity, DDR tool should be used to run the fine-tuned Data line byte delays.
  +
 
  +
  +
 
  +
* DDR does not works fine
  +
 
  +
1 check the pin muxing of the DDR signals against PCB schemtatics
  +
 
  +
2 check the voltages VDD-DDR, VREF_DDR, VDD-VTT on the PCB (also in DT of UbootSPL PMIC node)
  +
 
  +
3 check DDR timing (for DDR3 Speed bin / grade) against data sheet of DRAM
  +
 
  +
  +
How to run DDR tests and fine-tune the DDR timings with the CubeMX DDR tool tab ?
  +
 
  +
Adjust to PCB the UbootSPL Device Tree files (HSE,Uart trace,PMIC pin&Voltage) -should have the same TF-A nodes for these perif. Recompile UbootSPL (in Uboot folder, device tree files are shared between Uboot and UbootSPL). 
  +
Run tuning with CubeMx DDR tool tab.
  +
Behind CubeMx, CubeProgrammer feeds UART4 when bootrom boots on UART4 and loads & launches in SYRAM UbootSPL in DDR interactive mode. CubeMx DDR tool can then control DDR tuning & tests.
  +
 
  +
-Boot pin are set on serial.  "Connect" (in CubeMX DDR tool tab) via UART4 (or VCP with ST-link) to UbootSPL.
  +
 
  +
-Launch DDR tuning and tests DDR
  +
 
  +
-Save DDR parameters in Device tree DDR file.
  +
 
  +
Recompile TF-A with the generated DT DDR file to get TF-A with the finetuned parameters. Fine tune parameters are the over all the products (Depends on design not manufacturing).
  +
  +
 
  +
=== Check Uboot configuration ===
  +
 
  +
==== Check the bottom DDR address according to the DDR size ====
  +
 
  +
The botton address is define in Uboot DT
  +
 
  +
Ex for eval (8GBits) :
  +
 
  +
memory@c0000000 {
  +
    reg = <0xc0000000 0x40000000>;
  +
};
  +
 
  +
From a CubeMx Uboot dts file
  +
 
  +
Add:
  +
 
  +
-Same powers nodes as TF-A, according to the design (if STMPIC is on the design (I2C4 with PMIC node & pwr/pwr-regulators (for internal regulator supplies). In descrete no need to add these 2 nodes).
  +
 
  +
-same admmc1 node as TF-A, according to the SDMMC design (with or without levelshifter see pitfall)
  +
 
  +
=== Load Uboot in DDR ===
  +
 
  +
Similar methods to TF-A boot: from serial link with cubeprogrammer or from Sdcard (if available)
  +
 
  +
In .tsv , 2 first lines with binaries of TF-A (Id=0x1) and Uboot (id=0x3).
  +
 
  +
=== Kernel bring-up ===
  +
  +
Start from a dts file where all the peripheral nodes are disabled.
  +
 
  +
For each of them you have the device tree a first description in the wiki to add the adapted properties according to your PCB in the peripheral nodes.
  +
 
  +
Entry for the device tree description: article in the [[:Category:Device_tree_configuration|device tree configuration]] category
  +
 
  +
(You can also use the ST boards device tree files and relative schematics as example).
  +
 
  +
== Back ground knowledge ==
  +
  +
=== Reset signal on PowerOn sequence with ROM Code and PMIC ===
  +
When you power ON the STPMIC, it enters in internal POWER_UP state, NRST goes to 0 , when VDD and VDDCore are set and at the right level STPMIC goes from POWER_UP to internal POWER-START state and releases NRST but is maintained to 0 by MP1. The MP1 PowerOn Reset (POR) has detected the right level of VDD and VDDCORE and some delay elapsed the MP1 releases NRST, then ROM code is started. (NSRET PAD is open drain with internal pull-up) . PWR_ON goes to 1 once VDD is > POR/BOR threshold . PWR_ON should be 1 .
  +
 
  +
RM reference :      9.3.2 PWR supply system startup sequence
  +
 
  +
10.3.14 Power-on and wakeup sequences