Difference between revisions of "HSEM internal peripheral"
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Contents
1 Article purpose[edit]
The purpose of this article is to briefly introduce the hardware semaphore peripheral (HSEM) and its main features.
2 Peripheral overview[edit]
The peripheral hardware spinlock is used to provide synchronization and mutual exclusion between heterogeneous processors.
2.1 Features[edit]
Refer to the STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to see which features are implemented.
- 32 hardware semaphores are available on the platform.
- semaphores could be accessed by the Arm® Cortex®-A7 core and the Arm® Cortex®-M4
2.2 Security support[edit]
The hardware semaphores is a non-secure peripheral (under ETZPC control).
3 Peripheral usage and associated software[edit]
3.1 Boot time[edit]
The hardware semaphore is used at boot time for GPIO access protection between the Arm® Cortex®-A7 and Cortex®-M4 cores.
3.2 Runtime[edit]
3.2.1 Overview[edit]
The hardware spinlock can be used by:
- the Arm Cortex-A7 non-secure core to be controlled in Linux® by the hardware spinlock framework
- the Arm Cortex-M4 to be controlled in STM32Cube MPU Package by HSEM HAL driver
Notice that the Arm Cortex-A7 secure could also use the spinlock, but there is no such using yet in OpenSTLinux distribution.
3.2.2 Software frameworks[edit]
Internal peripherals software table template
| Domain | | | Linux hardware spinlock framework | HSEM HAL driver | |- |}
3.2.3 Peripheral configuration[edit]
The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the STM32CubeMX tool for all internal peripherals, and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article or, for Linux in the Hardware spinlock overview article.
The HSEM peripheral is shared between the Cortex-A and Cortex-M contexts, so a particular attention must be paid to have a complementary configuration on both contexts.
3.2.4 Peripheral assignment[edit]
It does not make sense to allocate HSEM to a single runtime execution context, that is why it is enabled by default for both cores in the STM32CubeMX.
Internal peripherals assignment table template
| rowspan="1" | Coprocessor | rowspan="1" | HSEM | HSEM | ✓ | ✓ | ✓ | |-
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<noinclude> {{ArticleMainWriter | BenjaminG}} {{ArticleApprovedVersion | BenjaminG | FabienD(Passed, 03Jan'19), ArnaudP(Passed 07Jan'19), Jean-ChristopheT(Passed with minor remarks, 03Jan'19) | No previous approved version | AnneJ - 09Jan'19 - 10251 | 10Jan'19}} [[Category:Core peripherals]] [[Category:Coprocessor management peripherals]]</noinclude> ==Article purpose== The purpose of this article is to briefly introduce the hardware semaphore peripheral (HSEM) and its main features. ==Peripheral overview== The peripheral hardware spinlock is used to provide synchronization and mutual exclusion between heterogeneous processors. ===Features=== Refer to the [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software components, introduced below, to see which features are implemented. * 32 hardware semaphores are available on the platform. * semaphores could be accessed by the Arm<sup>®</sup> Cortex<sup>®</sup>-A7 core and the Arm<sup>®</sup> Cortex<sup>®</sup>-M4 ===Security support=== The hardware semaphores is a '''non-secure''' peripheral (under [[ETZPC_internal_peripheral|ETZPC]] control). ==Peripheral usage and associated software== ===Boot time=== The hardware semaphore is used at boot time for GPIO access protection between the Arm<sup>®</sup> Cortex<sup>®</sup>-A7 and Cortex<sup>®</sup>-M4 cores. ===Runtime=== ====Overview==== The hardware spinlock can be used by: * the Arm Cortex-A7 non-secure core to be controlled in Linux<sup>®</sup> by the [[Hardware spinlock overview|hardware spinlock framework]] * the Arm Cortex-M4 to be controlled in STM32Cube MPU Package by [[STM32CubeMP1 architecture|HSEM HAL driver]] Notice that the Arm Cortex-A7 secure could also use the spinlock, but there is no such using yet in OpenSTLinux distribution. ====Software frameworks==== {{:Internal_peripherals_software_table_template}} | Domain | | | [[Hardware spinlock overview|Linux hardware spinlock framework]] | [[STM32CubeMP1 architecture|HSEM HAL driver]] | |- |} ====Peripheral configuration==== The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the [[STM32CubeMX]] tool for all internal peripherals, and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article or, for Linux in the [[Hardware spinlock overview]] article. The HSEM peripheral is shared between the Cortex-A and Cortex-M contexts, so a particular attention must be paid to have a complementary configuration on both contexts. ====Peripheral assignment==== It does not make sense to allocate HSEM to a single runtime execution context, that is why it is enabled by default for both cores in the [[STM32CubeMX]]. {{:Internal_peripherals_assignment_table_template}}<onlyinclude> | rowspan="1" | Coprocessor | rowspan="1" | [[HSEM internal peripheral|HSEM]] | HSEM | <span title="system peripheral" style="font-size:21px">✓</span> | <span title="system peripheral" style="font-size:21px">✓</span> | <span title="system peripheral" style="font-size:21px">✓</span> | |-</onlyinclude> |} <noinclude> [[Category:Core peripherals]] [[Category:Coprocessor management peripherals]] {{PublicationRequestId | 10251 | 2019-01-09 | AnneJ}} {{ArticleBasedOnModel | Internal peripheral article model}}</noinclude>
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==Article purpose== |
==Article purpose== |
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The purpose of this article is to briefly introduce the hardware semaphore peripheral (HSEM) and its main features. |
The purpose of this article is to briefly introduce the hardware semaphore peripheral (HSEM) and its main features. |
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| + | <noinclude> |
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| + | [[Category:Core peripherals]] |
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| + | [[Category:Coprocessor management peripherals]] |
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| + | {{PublicationRequestId | 10251 | 2019-01-09 | AnneJ}} |
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| + | {{ArticleBasedOnModel | Internal peripheral article model}} |
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| + | </noinclude> |
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