Difference between revisions of "GIC internal peripheral"

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1 Article purpose[edit]

The purpose of this article is to

  • briefly introduce the GIC peripheral (generic interrupt controller) and its main features
  • indicate the level of security supported by this hardware block
  • explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
  • explain, when needed, how to configure the GIC peripheral.

2 Peripheral overview[edit]

The GIC peripheral is the Arm® Cortex®-A7 interrupt controller. It is consequently not accessible from the Arm® Cortex®-M4 core.

2.1 Features[edit]

Refer to STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to know which features are really implemented.

2.2 Security support[edit]

The GIC is a secure peripheral (under ETZPC control).

3 Peripheral usage and associated software[edit]

3.1 Boot time[edit]

The GIC is configured by the FSBL (see Boot chains chain overview), mainly to define the routing of each interrupt to the secure or non-secure context at runtime: this configuration is further described in STM32MP15 interrupts article.

3.2 Runtime[edit]

3.2.1 Overview[edit]

The GIC can be allocated:

  • to the Arm® Cortex®-A7 secure core to be used under OP-TEE with the GIC OP-TEE driver (or TF-A secure monitor if the OP-TEE is not present)
  • or to the Arm® Cortex®-A7 non-secure core to be used under Linux® with the interrupts framework

3.2.2 Software frameworks[edit]

Domain Peripheral Software frameworks Comment
Cortex-A7
secure
(OP-TEE)
Cortex-A7
non-secure
(Linux)
Cortex-M4

(STM32Cube)
Core/Interrupts GIC OP-TEE GIC driver Linux interrupt framework

3.2.3 Peripheral configuration[edit]

The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration by itself can be performed via the STM32CubeMX tool for all internal peripherals. It can then be manually completed (especially for external peripherals) according to the information given in the corresponding software framework article.

3.2.4 Peripheral assignment[edit]

Internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

  • means that the peripheral can be assigned () to the given runtime context.
  • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain Peripheral Runtime allocation Comment
Instance Cortex-A7
secure
(OP-TEE)
Cortex-A7
non-secure
(Linux)
Cortex-M4

(STM32Cube)
Core/Interrupts GIC GIC

4 How to go further[edit]

Not applicable

5 References[edit]



<noinclude>

{{ArticleBasedOnModel| [[Internal peripheral article model]]}}
{{ArticleMainWriter|GeraldB}}
{{ ArticleApprovedVersion| GeraldB | LudovicB, AlexandreT, NathalieS |No previous approved version| AnneJ - 02Aug'18 - 8313 | 4Sep'18 }} 

[[Category:Interrupts peripherals]]

{{ReviewsComments|JCT 1840: alignment needed with the last version of the model [[Internal peripheral article model]]<br>

[[Category:ToBeAlignedWithModel]]
}}</noinclude>

==Article purpose==
The purpose of this article is to
* briefly introduce the '''GIC''' peripheral (generic interrupt controller) and its main features
* indicate the level of security supported by this hardware block
* explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
* explain, when needed, how to configure the GIC peripheral.

==Peripheral overview==
The '''GIC''' peripheral is the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 interrupt controller. It is consequently not accessible from the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-M4 core.<br />


===Features===
Refer to [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software components, introduced below, to know which features are really implemented.<br>


===Security support===
The GIC is a '''secure''' peripheral (under [[ETZPC_internal_peripheral|ETZPC]] control).

==Peripheral usage and associated software==
===Boot time===
The GIC is configured by the FSBL (see [[Boot chainschain overview]]), mainly to define the routing of each interrupt to the secure or non-secure context at runtime: this configuration is further described in [[STM32MP15 interrupts]] article.

===Runtime===
====Overview====
The GIC can be allocated:
* to the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 secure core to be used under OP-TEE with the GIC [[OP-TEE overview|OP-TEE]] driver (or [[TF-A overview|TF-A]] secure monitor if the OP-TEE is not present)
* or to the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure core to be used under Linux<sup>&reg;</sup> with the [[Interrupt overview|interrupts]] framework

====Software frameworks====
{{:Internal_peripherals_software_table_template}}
 | Core/Interrupts
 | [[GIC internal peripheral|GIC]]
 | [[OP-TEE_overview|OP-TEE GIC driver]]
 | [[Interrupt overview|Linux interrupt framework]]
 | 
 |
 |-
 |}

====Peripheral configuration====
The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration by itself can be performed via the [[STM32CubeMX]] tool for all internal peripherals. It can then be manually completed (especially for external peripherals) according to the information given in the corresponding software framework article.

====Peripheral assignment====
{{:Internal_peripherals_assignment_table_template}}<onlyinclude>

 | rowspan="1" | Core/Interrupts
 | rowspan="1" | [[GIC internal peripheral|GIC]]
 | GIC
 | <span title="system peripheral" style="font-size:21px"></span>

 | <span title="system peripheral" style="font-size:21px"></span>

 |
 |
 |-</onlyinclude>

 |}
==How to go further==
Not applicable

==References==<references/><noinclude>

[[Category:Interrupts peripherals]]
{{PublicationRequestId | 8313 | 2018-08-02 | AnneJ}}
{{ArticleBasedOnModel| Internal peripheral article model}}
{{ReviewsComments|JCT 1840: alignment needed with the last version of the model [[Contributors:Internal peripheral article model]]<br>

[[Category:ToBeAlignedWithModel]]
}}</noinclude>
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{{ArticleBasedOnModel| [[Internal peripheral article model]]}}
 
{{ArticleMainWriter|GeraldB}}
 
{{ ArticleApprovedVersion| GeraldB | LudovicB, AlexandreT, NathalieS |No previous approved version| AnneJ - 02Aug'18 - 8313 | 4Sep'18 }}
 
 
[[Category:Interrupts peripherals]]
 
 
{{ReviewsComments|JCT 1840: alignment needed with the last version of the model [[Internal peripheral article model]]<br>
 
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==Article purpose==
 
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==Peripheral usage and associated software==
 
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===Boot time===
 
===Boot time===
The GIC is configured by the FSBL (see [[Boot chains overview]]), mainly to define the routing of each interrupt to the secure or non-secure context at runtime: this configuration is further described in [[STM32MP15 interrupts]] article.
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The GIC is configured by the FSBL (see [[Boot chain overview]]), mainly to define the routing of each interrupt to the secure or non-secure context at runtime: this configuration is further described in [[STM32MP15 interrupts]] article.
   
 
===Runtime===
 
===Runtime===
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==How to go further==
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<noinclude>
Not applicable
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[[Category:Interrupts peripherals]]
 
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{{PublicationRequestId | 8313 | 2018-08-02 | AnneJ}}
==References==
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{{ArticleBasedOnModel| Internal peripheral article model}}
<references/>
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{{ReviewsComments|JCT 1840: alignment needed with the last version of the model [[Contributors:Internal peripheral article model]]<br>
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[[Category:ToBeAlignedWithModel]]
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}}
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