Difference between revisions of "GIC internal peripheral"

[quality revision] [quality revision]
(Merge articles)
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Applicable for STM32MP13x lines, STM32MP15x lines

1 Article purpose[edit]

The purpose of this article is to

  • briefly introduce the GIC peripheral (generic interrupt controller) and its main features
  • indicate the level of security supported by this hardware block
  • explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
  • explain, when needed, how to configure the GIC peripheral.

2 Peripheral overview[edit]

The GIC peripheral is the Arm® Cortex®-A7 interrupt controller.
It is consequently not accessible from the Arm® Cortex®-M4 core on STM32MP15x lines More info.png.

2.1 Features[edit]

Refer to STM32MP13 reference manuals or STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to know which features are really implemented.

2.2 Security support[edit]

The GIC is a secure peripheral (under ETZPC control).

3 Peripheral usage and associated software[edit]

3.1 Boot time[edit]

The GIC is configured by the FSBL (see Boot chain overview), mainly to define the routing of each interrupt to the secure or non-secure context at runtime.

3.2 Runtime[edit]

3.2.1 Overview[edit]

The GIC can be allocatedis shared between:

  • to the Arm® Cortex®-A7 secure core to be used under OP-TEE with the GIC OP-TEE driver (or TF-A secure monitor if the OP-TEE is not present)
  • or to the Arm® Cortex®-A7 non-secure core to be used under Linux® with the interrupts framework

3.2.2 Software frameworks[edit]

Internal peripherals software table template

| Core/Interrupts
| GIC
| OP-TEE GIC driver
| Linux interrupt framework
| 
|
|-
|}

3.2.2.1 On STM32MP13x lines Warning.png[edit]
Domain Peripheral Software components Comment
OP-TEE Linux
Core/Interrupts GIC OP-TEE GIC driver Linux interrupt framework
3.2.2.2 On STM32MP15x lines More info.png[edit]
Domain Peripheral Software components Comment
OP-TEE Linux STM32Cube
Core/Interrupts GIC OP-TEE GIC driver Linux interrupt framework

3.2.3 Peripheral configuration[edit]

The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration by itself can be performed via the STM32CubeMX tool for all internal peripherals. It can then be manually completed (especially for external peripherals) according to the information given in the corresponding software framework article.

3.2.4 Peripheral assignment[edit]

Internal peripherals assignment table template

| rowspan="1" | Core/Interrupts
| rowspan="1" | GIC
| GIC
| 
| 
|
|
|-

|}

3.2.4.1 On STM32MP13x lines Warning.png[edit]

Click on the right to expand the legend...

STM32MP13IPsOverview.png

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

  • means that the peripheral can be assigned () to the given runtime context.
  • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
  • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP13 reference manuals.

Domain Peripheral Runtime allocation Comment
Instance Cortex-A7
secure
(OP-TEE)
Cortex-A7
non-secure
(Linux)
Core/Interrupts GIC GIC
3.2.4.2 On STM32MP15x lines More info.png[edit]

Click on the right to expand the legend...

STM32MP15 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

  • means that the peripheral can be assigned () to the given runtime context.
  • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
  • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain Peripheral Runtime allocation Comment
Instance Cortex-A7
secure
(OP-TEE)
Cortex-A7
non-secure
(Linux)
Cortex-M4

(STM32Cube)
Core/Interrupts GIC GIC



==<noinclude>{{ApplicableFor
|MPUs list=STM32MP13x, STM32MP15x
|MPUs checklist=STM32MP13x, STM32MP15x
}}</noinclude>

==Article purpose==
The purpose of this article is to
* briefly introduce the '''GIC''' peripheral (generic interrupt controller) and its main features
* indicate the level of security supported by this hardware block
* explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
* explain, when needed, how to configure the GIC peripheral.

==Peripheral overview==
The '''GIC''' peripheral is the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 interrupt controller. <br>
It is consequently not accessible from the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-M4 core on {{MicroprocessorDevice | device=15}}.<br />


===Features===
Refer to [[STM32MP13 resources#Reference manuals|STM32MP13 reference manuals]] or [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software components, introduced below, to know which features are really implemented.<br>


===Security support===
The GIC is a '''secure''' peripheral (under [[ETZPC_internal_peripheral|ETZPC]] control).

==Peripheral usage and associated software==
===Boot time===
The GIC is configured by the FSBL (see [[Boot chain overview]]), mainly to define the routing of each interrupt to the secure or non-secure context at runtime.

===Runtime===
====Overview====
The GIC can be allocated:
* to is shared between:
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 secure core to be used under OP-TEE with the GIC [[OP-TEE overview|OP-TEE]] driver (or [[TF-A overview|TF-A]] secure monitor if the OP-TEE is not present)
* or to the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure core to be used under Linux<sup>&reg;</sup> with the [[Interrupt overview|interrupts]] framework

====Software frameworks===={{:Internal===== On {{MicroprocessorDevice | device=13}} =====
{{:STM32MP13 internal_peripherals_software_table_template}}
 | Core/Interrupts
 | [[GIC internal peripheral|GIC]]
 | [[OP-TEE_overview|OP-TEE GIC driver]]
 | [[Interrupt overview|Linux interrupt framework]]
 | |
 |-
 ||-
 |}
===== On {{MicroprocessorDevice | device=15}} =====
{{:STM32MP15_internal_peripherals_software_table_template}}
 | Core/Interrupts
 | [[GIC internal peripheral|GIC]]
 | [[OP-TEE_overview|OP-TEE GIC driver]]
 | [[Interrupt overview|Linux interrupt framework]]
 | 
 |
 |-
 |}

====Peripheral configuration====
The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration by itself can be performed via the [[STM32CubeMX]] tool for all internal peripherals. It can then be manually completed (especially for external peripherals) according to the information given in the corresponding software framework article.

====Peripheral assignment===={{:Internal_===== On {{MicroprocessorDevice | device=13}} =====
{{:STM32MP13_internal_peripherals_assignment_table_template}}<onlyinclude><section begin=stm32mp13 />

 | rowspan="1" | Core/Interrupts
 | rowspan="1" | [[GIC internal peripheral|GIC]]
 | GIC
 | <span title="system peripheral" style="font-size:21px"></span>

 | <span title="system peripheral" style="font-size:21px"></span>

 |
 |

 |-</onlyinclude>-<section end=stm32mp13 />

 |}
===== On {{MicroprocessorDevice | device=15}} =====
{{:STM32MP15_internal_peripherals_assignment_table_template}}<section begin=stm32mp15 />

 | rowspan="1" | Core/Interrupts
 | rowspan="1" | [[GIC internal peripheral|GIC]]
 | GIC
 | <span title="system peripheral" style="font-size:21px"></span>

 | <span title="system peripheral" style="font-size:21px"></span>

 |
 |
 |-<section end=stm32mp15 />

 |}
<noinclude>

[[Category:Interrupts peripherals]]
{{PublicationRequestId | 8313 | 2018-08-02 | AnneJ}}
{{ArticleBasedOnModel| Internal peripheral article model}}
{{ReviewsComments|JCT 1840: alignment needed with the last version of the model [[Contributors:Internal peripheral article model]]<br>

[[Category:ToBeAlignedWithModel]]
}}</noinclude>
(6 intermediate revisions by 2 users not shown)
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  +
<noinclude>{{ApplicableFor
  +
|MPUs list=STM32MP13x, STM32MP15x
  +
|MPUs checklist=STM32MP13x, STM32MP15x
  +
}}</noinclude>
 
==Article purpose==
 
==Article purpose==
 
The purpose of this article is to
 
The purpose of this article is to
 
* briefly introduce the '''GIC''' peripheral (generic interrupt controller) and its main features
 
* briefly introduce the '''GIC''' peripheral (generic interrupt controller) and its main features
 
* indicate the level of security supported by this hardware block
 
* indicate the level of security supported by this hardware block
* explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
+
* explain how each instance can be allocated to the runtime contexts and linked to the corresponding software components
 
* explain, when needed, how to configure the GIC peripheral.
 
* explain, when needed, how to configure the GIC peripheral.
   
 
==Peripheral overview==
 
==Peripheral overview==
The '''GIC''' peripheral is the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 interrupt controller. It is consequently not accessible from the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-M4 core.<br />
+
The '''GIC''' peripheral is the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 interrupt controller. <br>
  +
It is consequently not accessible from the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-M4 core on {{MicroprocessorDevice | device=15}}.<br />
   
 
===Features===
 
===Features===
Refer to [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software components, introduced below, to know which features are really implemented.<br>
+
Refer to [[STM32MP13 resources#Reference manuals|STM32MP13 reference manuals]] or [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software components, introduced below, to know which features are really implemented.<br>
   
 
===Security support===
 
===Security support===
Line 21: Line 26:
 
===Runtime===
 
===Runtime===
 
====Overview====
 
====Overview====
The GIC can be allocated:
+
The GIC is shared between:
* to the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 secure core to be used under OP-TEE with the GIC [[OP-TEE overview|OP-TEE]] driver (or [[TF-A overview|TF-A]] secure monitor if the OP-TEE is not present)
+
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 secure core to be used under OP-TEE with the GIC [[OP-TEE overview|OP-TEE]] driver (or [[TF-A overview|TF-A]] secure monitor if the OP-TEE is not present)
* or to the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure core to be used under Linux<sup>&reg;</sup> with the [[Interrupt overview|interrupts]] framework
+
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure core to be used under Linux<sup>&reg;</sup> with the [[Interrupt overview|interrupts]] framework
   
 
====Software frameworks====
 
====Software frameworks====
{{:Internal_peripherals_software_table_template}}
+
===== On {{MicroprocessorDevice | device=13}} =====
  +
{{:STM32MP13 internal_peripherals_software_table_template}}
  +
| Core/Interrupts
  +
| [[GIC internal peripheral|GIC]]
  +
| [[OP-TEE_overview|OP-TEE GIC driver]]
  +
| [[Interrupt overview|Linux interrupt framework]]
  +
|
  +
|-
  +
|}
  +
===== On {{MicroprocessorDevice | device=15}} =====
  +
{{:STM32MP15_internal_peripherals_software_table_template}}
 
  | Core/Interrupts
 
  | Core/Interrupts
 
  | [[GIC internal peripheral|GIC]]
 
  | [[GIC internal peripheral|GIC]]
Line 40: Line 55:
   
 
====Peripheral assignment====
 
====Peripheral assignment====
{{:Internal_peripherals_assignment_table_template}}
+
===== On {{MicroprocessorDevice | device=13}} =====
<onlyinclude>
+
{{:STM32MP13_internal_peripherals_assignment_table_template}}
  +
<section begin=stm32mp13 />
  +
| rowspan="1" | Core/Interrupts
  +
| rowspan="1" | [[GIC internal peripheral|GIC]]
  +
| GIC
  +
| <span title="system peripheral" style="font-size:21px">✓</span>
  +
| <span title="system peripheral" style="font-size:21px">✓</span>
  +
|
  +
|-
  +
<section end=stm32mp13 />
  +
|}
  +
===== On {{MicroprocessorDevice | device=15}} =====
  +
{{:STM32MP15_internal_peripherals_assignment_table_template}}
  +
<section begin=stm32mp15 />
 
  | rowspan="1" | Core/Interrupts
 
  | rowspan="1" | Core/Interrupts
 
  | rowspan="1" | [[GIC internal peripheral|GIC]]
 
  | rowspan="1" | [[GIC internal peripheral|GIC]]
Line 50: Line 78:
 
  |
 
  |
 
  |-
 
  |-
</onlyinclude>
+
<section end=stm32mp15 />
 
  |}
 
  |}