Difference between revisions of "FMC internal peripheral"

[quality revision] [quality revision]
m
m (Peripheral configuration)
 
Applicable for STM32MP13x lines, STM32MP15x lines

1 Article purpose[edit]

The purpose of this article is to:

  • briefly introduce the FMC peripheral and its main features
  • indicate the level of security supported by this hardware block
  • explain how each instance can be allocated to the runtime contexts and linked to the corresponding software components
  • explain , when needed, how to configure the FMC peripheral if necessary.

2 Peripheral overview[edit]

The FMC peripheral includes two memory controllers:

  • The NOR/PSRAM memory controller
  • The NAND memory controller.

2.1 NOR/PSRAM memory controller (or external bus interface controller)[edit]

The FMC NOR/PSRAM memory controller is used to interface static memory devices, but it is also used to interface Ethernet devices, LCD devices, .... . and so on.

The FMC NOR/PSRAM controller generates the appropriate signal timings to drive the following types of memories:

  • Asynchronous SRAM, FRAM and ROM
    • 8 bits
    • 16 bits
  • PSRAM (CellularRAM™)
    • Asynchronous mode
    • Burst mode for synchronous accesses with configurable option to split burst access when crossing boundary page for CRAM 1.5.
    • Multiplexed or non-multiplexed
  • NOR Flash memory
    • Asynchronous mode
    • Burst mode for synchronous accesses
    • Multiplexed or non-multiplexed

The FMC NOR/PSRAM controller supports a wide range of devices through programmable timings among which.
Among those programmable timings, there are:

  • Programmable wait states (up to 15)
  • Programmable bus turnaround cycles (up to 15)
  • Programmable output enable and write enable delays (up to 15)
  • Independent read and write timings and protocol to support the widest variety of memories and timings
  • Programmable continuous clock output.

The FMC NOR/PSRAM controller also supports up to four external devices.

2.2 NAND Flash controller[edit]

The FMC NAND Flash controller is used to interface STM32 MPU with SLC 8-bit or 16-bit NAND Flash memory devices.

The FMC NAND Flash controller supports:

  • Programmable error correction capability (ECC) using BCH8 code, BCH4 code or Hamming code
  • Programmable page size of 2048, 4096 and 8192 bytes
  • Programmable memory timings
  • Multiple dice per package.

2.3 Features[edit]

Refer to STM32MP13 reference manuals or STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to know which features are really implemented.

2.4 Security support[edit]

2.4.1 On STM32MP13x lines Warning.png[edit]

The FMC is a secure peripheral (under ETZPC control).

2.4.2 On STM32MP15x lines More info.png[edit]

The FMC is a non-secure peripheral.

3 Peripheral usage and associated software[edit]

3.1 Boot time[edit]

The FMC NAND Flash controller is the boot device that supports serial boot for Flash programming with STM32CubeProgrammer.

3.2 Runtime[edit]

3.2.1 Overview[edit]

The FMC peripheral can be allocated to:

  • the Arm® Cortex®-A7 secure context, on STM32MP13x lines Warning.png only, but this is not supported in OpenSTLinux.

or

  • the Arm® Cortex®-A7 non-secure core to be controlled in Linux® by the MTD framework.

or

  • the Arm® Cortex®-M4, on STM32MP15x lines More info.png only, to be controlled in STM32Cube MPU Package by FMC HAL driver.

Chapter #Peripheral assignment describes which instance can be assigned to which context.

3.2.2 Software frameworks[edit]

3.2.2.1 On STM32MP13x lines Warning.png[edit]
Domain Peripheral Software components Comment
OP-TEE Linux
Mass storage FMC Linux MTD Framework
3.2.2.2 On STM32MP15x lines More info.png[edit]
Domain Peripheral Software components Comment
OP-TEE Linux STM32Cube
Mass storage FMC Linux MTD Framework STM32Cube FMC driver

3.2.3 Peripheral configuration[edit]

The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the STM32CubeMX tool for all internal peripherals, and then manually completed (particularly for external peripherals), according to the given information given in the corresponding software framework article.

For Linux kernel configuration, please refer to FMC device tree configuration.

3.2.4 Peripheral assignment[edit]

3.2.4.1 On STM32MP13x lines Warning.png[edit]

Click on the right to expand the legend...

STM32MP13IPsOverview.png

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

  • means that the peripheral can be assigned () to the given runtime context.
  • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
  • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP13 reference manuals.

Domain Peripheral Runtime allocation Comment
Instance Cortex-A7
secure
(OP-TEE)
Cortex-A7
non-secure
(Linux)
Mass storage FMC FMC Assignment (single choice)
3.2.4.2 On STM32MP15x lines More info.png[edit]

Click on the right to expand the legend...

STM32MP15 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

  • means that the peripheral can be assigned () to the given runtime context.
  • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
  • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain Peripheral Runtime allocation Comment
Instance Cortex-A7
secure
(OP-TEE)
Cortex-A7
non-secure
(Linux)
Cortex-M4

(STM32Cube)
Mass storage FMC FMC Assignment (single choice)

4 How to go further[edit]

5 References[edit]




<noinclude>{{ApplicableFor
|MPUs list=STM32MP13x, STM32MP15x
|MPUs checklist=STM32MP13x,STM32MP15x
}}</noinclude>


==Article purpose==
The purpose of this article is to:

* briefly introduce the FMC  peripheral and its main features
* indicate the level of security supported by this hardware block
* explain how each instance can be allocated to the runtime contexts and linked to the corresponding software components
* explain, when needed,  how to configure the FMC peripheral if necessary.

==Peripheral overview==
The '''FMC''' peripheral includes two memory controllers:
* The NOR/PSRAM memory controller
* The NAND memory controller.


===NOR/PSRAM memory controller (or external bus interface controller)===
The '''FMC''' NOR/PSRAM memory controller is used to interface static memory devices, but it is also used to interface Ethernet devices, LCD devices, .... and so on.<br><br>

The '''FMC''' NOR/PSRAM controller generates the appropriate signal timings to drive the following types of memories:
* Asynchronous SRAM, FRAM and ROM
** 8 bits
**16 bits
* PSRAM (CellularRAM™)
** Asynchronous mode
**Burst mode for synchronous accesses with configurable option to split burst access when crossing boundary page for CRAM 1.5.
**Multiplexed or non-multiplexed
* NOR Flash memory
** Asynchronous mode
**Burst mode for synchronous accesses
**Multiplexed or non-multiplexed
The '''FMC''' NOR/PSRAM controller supports a wide range of devices through programmable timings among which. <br>Among those programmable timings, there are:
* Programmable wait states (up to 15)
* Programmable bus turnaround cycles (up to 15)
* Programmable output enable and write enable delays (up to 15)
* Independent read and write timings and protocol to support the widest variety of memories and timings
* Programmable continuous clock output.
The '''FMC''' NOR/PSRAM controller also supports up to four external devices.

===NAND Flash controller===
The '''FMC''' NAND Flash controller is used to interface STM32 MPU with SLC 8-bit or 16-bit NAND Flash memory devices. <br><br>

The '''FMC''' NAND Flash controller supports:
* Programmable error correction capability (ECC) using BCH8 code, BCH4 code or Hamming code
* Programmable page size of 2048, 4096 and 8192 bytes
* Programmable memory timings
* Multiple dice per package. <br>


===Features===
Refer to [[STM32MP13 resources#Reference manuals|STM32MP13 reference manuals]] or [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software components, introduced below, to know which features are really implemented.<br>


===Security support===
==== On {{MicroprocessorDevice | device=13}} ====
The FMC is a '''secure''' peripheral (under [[ETZPC_internal_peripheral|ETZPC]] control).
==== On {{MicroprocessorDevice | device=15}} ====
The FMC is a '''non-secure''' peripheral.

==Peripheral usage and associated software==
===Boot time===
The FMC NAND Flash controller is the boot device that supports serial boot for Flash programming with [[STM32CubeProgrammer]].

===Runtime===
====Overview====
The FMC peripheral can be allocated to:
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 secure context, on {{MicroprocessorDevice | device=13}} only, but this is not supported in OpenSTLinux.
or
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure core to be controlled in Linux<sup>&reg;</sup> by the [[MTD overview|MTD]] framework.

or
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-M4, on {{MicroprocessorDevice | device=15}} only, to be controlled in STM32Cube MPU Package by [[STM32CubeMP1 architecture|FMC HAL driver]].


Chapter [[#Peripheral assignment]] describes which instance can be assigned to which context.

====Software frameworks====
===== On {{MicroprocessorDevice | device=13}} =====
{{:STM32MP13 internal peripherals software table template}}
 | Mass storage
 | [[FMC internal peripheral|FMC]]
 | 
 | [[MTD overview|Linux MTD Framework]]
 |
 |-
 |}
===== On {{MicroprocessorDevice | device=15}} =====
{{:STM32MP15_internal_peripherals_software_table_template}}
 | Mass storage
 | [[FMC internal peripheral|FMC]]
 | 
 | [[MTD overview|Linux MTD Framework]]
 | [[STM32CubeMP1 architecture|STM32Cube FMC driver]]
 |
 |-
 |}

====Peripheral configuration====
The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the [[STM32CubeMX]] tool for all internal peripherals, and then manually completed (particularly for external peripherals), according to the given information given in the corresponding software framework article.

For Linux kernel configuration, please refer to [[FMC device tree configuration]].


====Peripheral assignment====
===== On {{MicroprocessorDevice | device=13}} =====
{{:STM32MP13_internal_peripherals_assignment_table_template}}<section begin=stm32mp13 />

 | rowspan="1" | Mass storage
 | rowspan="1" | [[FMC internal peripheral|FMC]]
 | FMC
 | <span title="assignable peripheral but not supported" style="font-size:21px"></span>

 | <span title="assignable peripheral" style="font-size:21px"></span>

 | Assignment (single choice)
 |-<section end=stm32mp13 />

 |}
===== On {{MicroprocessorDevice | device=15}} =====
{{:STM32MP15_internal_peripherals_assignment_table_template}}<section begin=stm32mp15 />

 | rowspan="1" | Mass storage
 | rowspan="1" | [[FMC internal peripheral|FMC]]
 | FMC
 |
 | <span title="assignable peripheral" style="font-size:21px"></span>

 | <span title="assignable peripheral" style="font-size:21px"></span>

 | Assignment (single choice)
 |-<section end=stm32mp15 />

 |}

==How to go further==

==References==<references/>

<noinclude>

{{ArticleBasedOnModel | Internal peripheral article model}}{{PublicationRequestId | 24638 | 2022-09-26 | }}[[Category:Mass storage peripherals]]</noinclude>
(8 intermediate revisions by 2 users not shown)
Line 5: Line 5:
   
 
==Article purpose==
 
==Article purpose==
The purpose of this article is to
+
The purpose of this article is to:
 
* briefly introduce the FMC  peripheral and its main features
 
* briefly introduce the FMC  peripheral and its main features
 
* indicate the level of security supported by this hardware block
 
* indicate the level of security supported by this hardware block
 
* explain how each instance can be allocated to the runtime contexts and linked to the corresponding software components
 
* explain how each instance can be allocated to the runtime contexts and linked to the corresponding software components
* explain, when needed, how to configure the FMC peripheral.
+
* explain how to configure the FMC peripheral if necessary.
   
 
==Peripheral overview==
 
==Peripheral overview==
 
The '''FMC''' peripheral includes two memory controllers:
 
The '''FMC''' peripheral includes two memory controllers:
 
* The NOR/PSRAM memory controller
 
* The NOR/PSRAM memory controller
* The NAND memory controller
+
* The NAND memory controller.
   
 
===NOR/PSRAM memory controller (or external bus interface controller)===
 
===NOR/PSRAM memory controller (or external bus interface controller)===
The '''FMC''' NOR/PSRAM memory controller is used to interface static memory devices, but it is also used to interface Ethernet devices, LCD devices, .... .
+
The '''FMC''' NOR/PSRAM memory controller is used to interface static memory devices, but it is also used to interface Ethernet devices, LCD devices, and so on.
 
<br><br>
 
<br><br>
 
The '''FMC''' NOR/PSRAM controller generates the appropriate signal timings to drive the following types of memories:
 
The '''FMC''' NOR/PSRAM controller generates the appropriate signal timings to drive the following types of memories:
Line 31: Line 31:
 
**Burst mode for synchronous accesses
 
**Burst mode for synchronous accesses
 
**Multiplexed or non-multiplexed
 
**Multiplexed or non-multiplexed
The '''FMC''' NOR/PSRAM controller supports a wide range of devices through programmable timings among which:
+
The '''FMC''' NOR/PSRAM controller supports a wide range of devices through programmable timings. <br>Among those programmable timings, there are:
 
* Programmable wait states (up to 15)
 
* Programmable wait states (up to 15)
 
* Programmable bus turnaround cycles (up to 15)
 
* Programmable bus turnaround cycles (up to 15)
Line 37: Line 37:
 
* Independent read and write timings and protocol to support the widest variety of memories and timings
 
* Independent read and write timings and protocol to support the widest variety of memories and timings
 
* Programmable continuous clock output.
 
* Programmable continuous clock output.
The '''FMC''' NOR/PSRAM controller supports up to four external devices.
+
The '''FMC''' NOR/PSRAM controller also supports up to four external devices.
+
 
 
===NAND Flash controller===
 
===NAND Flash controller===
 
The '''FMC''' NAND Flash controller is used to interface STM32 MPU with SLC 8-bit or 16-bit NAND Flash memory devices. <br><br>
 
The '''FMC''' NAND Flash controller is used to interface STM32 MPU with SLC 8-bit or 16-bit NAND Flash memory devices. <br><br>
Line 65: Line 65:
 
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 secure context, on {{MicroprocessorDevice | device=13}} only, but this is not supported in OpenSTLinux.
 
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 secure context, on {{MicroprocessorDevice | device=13}} only, but this is not supported in OpenSTLinux.
 
or
 
or
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure core to be controlled in Linux<sup>&reg;</sup> by the [[MTD overview|MTD]] framework
+
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure core to be controlled in Linux<sup>&reg;</sup> by the [[MTD overview|MTD]] framework.
 
or
 
or
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-M4, on {{MicroprocessorDevice | device=15}} only, to be controlled in STM32Cube MPU Package by [[STM32CubeMP1 architecture|FMC HAL driver]]
+
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-M4, on {{MicroprocessorDevice | device=15}} only, to be controlled in STM32Cube MPU Package by [[STM32CubeMP1 architecture|FMC HAL driver]].
   
 
Chapter [[#Peripheral assignment]] describes which instance can be assigned to which context.
 
Chapter [[#Peripheral assignment]] describes which instance can be assigned to which context.
Line 93: Line 93:
   
 
====Peripheral configuration====
 
====Peripheral configuration====
The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the [[STM32CubeMX]] tool for all internal peripherals, and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article.
+
The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the [[STM32CubeMX]] tool for all internal peripherals, and then manually completed (particularly for external peripherals), according to the given information in the corresponding software framework article.
   
For Linux kernel configuration, please refer to [[FMC device tree configuration]]
+
For Linux kernel configuration, please refer to [[FMC device tree configuration]].
   
 
====Peripheral assignment====
 
====Peripheral assignment====
Line 131: Line 131:
 
<noinclude>
 
<noinclude>
 
{{ArticleBasedOnModel | Internal peripheral article model}}
 
{{ArticleBasedOnModel | Internal peripheral article model}}
  +
{{PublicationRequestId | 24638 | 2022-09-26 | }}
 
[[Category:Mass storage peripherals]]
 
[[Category:Mass storage peripherals]]
 
</noinclude>
 
</noinclude>