Difference between revisions of "Ethernet device tree configuration"

[quality revision] [checked revision]
m (How to enable and use Wake on LAN (WoL) from PHY)
m (How to enable and use Wake on LAN (WoL) from PHY)
 
Applicable for STM32MP13x lines, STM32MP15x lines

1 Article purpose[edit]

This article explains how to configure the Ethernet when it is assigned to the Linux® OS. In that this case, it is controlled by the Ethernet framework.

The configuration is performed using the device tree mechanism that . This provides a hardware description of the Ethernet peripheral , used by the STM32 DWMAC driver.

2 DT bindings documentation[edit]

The Ethernet is a multifunction device.

Each function is represented by a separate binding document:

  • "Generic" Ethernet device tree bindings [1]
  • specific Specific STM32 ETH device tree bindings[2]

3 DT configuration[edit]

This hardware description is a combination of the STM32 microprocessor device tree files (.dtsi extension) and board device tree files (.dts extension). See the Device tree for an explanation of the device tree file split.

3.1 DT configuration (STM32 level)[edit]

Ethernet peripheral nodes are located in

  • for STM32MP13x lines Warning.png in stm32mp131.dtsi [3] file,
  • for STM32MP15x lines More info.png in stm32mp151.dtsi [4] file,

In this file, the status must be set to disabled, and some required properties such asthe following properties must be set:

  • Physical base address and size of the device register map
  • STM32 DWMAC interrupts
  • stmmaceth clock and Rx, Tx clocks

This is a set of properties that may not vary for a given STM32MP device, such as: register addresses, interrupts, clocks, ...

ethernet0: ethernet@5800a000 {
	compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
	reg = <0x5800a000 0x2000>;
	reg-names = "stmmaceth";
                              <&exti 70 IRQ_TYPE_LEVEL_HIGH>;
        interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
        interrupt-names = "macirq",
                          "eth_wake_irq";
	clock-names = "stmmaceth",
		      "mac-clk-tx",
		      "mac-clk-rx",
		      "eth-ck",
		      "ethstp";
	clocks = <&rcc ETHMAC>,
		 <&rcc ETHTX>,
		 <&rcc ETHRX>,
		 <&rcc ETHCK_K>,
		 <&rcc ETHSTP>;
	st,syscon = <&syscfg 0x4>;
	snps,mixed-burst;
	snps,pbl = <2>;
        snps,en-tx-lpi-clockgating;
	snps,axi-config = <&stmmac_axi_config_0>;
	snps,tso;
	power-domains = <&pd_core>;
	status = "disabled";
};

The required and optional properties are fully described in the bindings files.

Warning white.png Warning
This device tree part is related to STM32 microprocessors. It must be kept as is, without being modified by the end-user.

3.2 Ethernet DT configuration (board level)[edit]

Warning white.png Warning
These DT are same between U-Boot and kernel OS

The device tree board file (.dts) contains all hardware configurations related to board design. The DT node ("ethernet") should must be updated to:

  • Enable the Ethernet block by setting status = "okay".
  • Configure the pins in use via pinctrl, through pinctrl-0 (default pins), pinctrl-1 (sleep pins) and pinctrl-names.
  • Configure Ethernet interface used phy-mode = "rgmii"., (rmii, mii, gmii).
  • Configure Ethernet max speed max-speed = <1000>"..
&ethernet0 {
	status = "okay";
	pinctrl-0 = <&ethernet0_rgmii_pins_a>;
	pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
	pinctrl-names = "default", "sleep";
	phy-mode = "rgmii";
	max-speed = <1000>;
	phy-handle = <&phy0>;

	mdio0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,dwmac-mdio";
		phy0: ethernet-phy@1 {
			reg = <1>;
		};
	};
};

3.3 DT configuration examples at board level[edit]

The example below shows how to configure and enable an Ethernet instance

&ethernet0 {
   status = "okay";                             /* enable ethernet0 */ 
   pinctrl-0 = <&ethernet0_rmii_pins_a>;        /* configure pinctrl modes for ethernet0 */
   pinctrl-1 = <&ethernet0_rmii_pins_sleep_a>;  /* configure ethernet0_rmii_pins_sleep_a as sleep pinctrl configuration for ethernet0 */
   pinctrl-names = "default", "sleep";
   phy-mode = "rmii";                           /* configure ethernet phy mode for ethernet0 */
   max-speed = <100>;                           /* configure ethernet max speed for ethernet0 */
   phy-handle = <&phy0>;
   
   mdio0 {
       #address-cells = <1>;
       #size-cells = <0>;
       compatible = "snps,dwmac-mdio";
       phy0: ethernet-phy@1 {
           reg = <1>;                           /* configure ethernet phy @ for ethernet0 */
       };
   };
};

How to configure Ethernet for :

3.3.1 RMII with Crystal on PHY (Reference clock (standard RMII clock name) is provided by a Phy Crystal)[edit]

   &ethernet0 {
       status = "okay";
       pinctrl-0 = <&ethernet0_rmii_pins_a>;
       pinctrl-1 = <&ethernet0_rmii_pins_sleep_a>;
       pinctrl-names = "default", "sleep";
       phy-mode = "rmii";
       max-speed = <100>;
       phy-handle = <&phy0>;
       mdio0 {
               #address-cells = <1>;
               #size-cells = <0>;
               compatible = "snps,dwmac-mdio";
               phy0: ethernet-phy@0 {
                       reg = <0>;
               };
       };
   };

3.3.2 RMII with 25MHz on ETH_CLK (no PHY Crystal), REF_CLK from PHY (Reference clock (standard RMII clock name) is provided by a PHY)[edit]

   &ethernet0 {
       status = "okay";
       pinctrl-0 = <&ethernet0_rmii_pins_a>;
       pinctrl-1 = <&ethernet0_rmii_pins_sleep_a>;
       pinctrl-names = "default", "sleep";
       phy-mode = "rmii";
       max-speed = <100>;
       phy-handle = <&phy0>;
       mdio0 {
               #address-cells = <1>;
               #size-cells = <0>;
               compatible = "snps,dwmac-mdio";
               phy0: ethernet-phy@0 {
                       reg = <0>;
               };
       };
   };

+ update stm32mp15-pinctrl.dtsi [5] to add ETHCK pin in ethernet0_rmii_pins_* node:
For example:

 <STM32_PINMUX('G', 8, AF2)>, /* ETH_RMII_ETHCK */

+ Need also to update TFA devicetree to generate 25Mhz clock (from PLL4P or PLL3Q):
for example if PLL4P in ed1 board: update fdts/stm32mp15xx-edx.dtsi

st,pkcs = <
 CLK_CKPER_HSE
 CLK_FMC_ACLK
 CLK_QSPI_ACLK
 - CLK_ETH_DISABLED
 + CLK_ETH_PLL4P
...
 /* VCO = 600.0 MHz => P = 25, Q = 50, R = 50 */
   pll4: st,pll@3 {
     compatible = "st,stm32mp1-pll";
     reg = <3>;
     cfg = < 1 49 23 11 11 PQR(1,1,1) >;
 };

3.3.3 RMII with 50MHz on ETH_CLK (no PHY Crystal), internal REF_CLK from RCC (Reference clock (standard RMII clock name) is provided by a an RCC SoC internal clock)[edit]

For ecosystem release ≤ v3.0.0 , only for STM32MP15x lines More info.png

   ethernet0: ethernet@5800a000 {
       compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
       reg = <0x5800a000 0x2000>;
       reg-names = "stmmaceth";
       interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
                             <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
                             <&exti 70 1>;
       interrupt-names = "macirq",
                         "eth_wake_irq",
                         "stm32_pwr_wakeup";
       clock-names = "stmmaceth",
                      "mac-clk-tx",
                      "mac-clk-rx",
                      "eth-ck",
                      "ethstp";
       clocks = <&rcc ETHMAC>,
                      <&rcc ETHTX>,
                      <&rcc ETHRX>,
                      <&rcc ETHCK_K>,
                      <&rcc ETHSTP>;
       st,syscon = <&syscfg 0x4>;
       snps,mixed-burst;
       snps,pbl = <2>;
       snps,en-tx-lpi-clockgating;
       st,eth_ref_clk_sel;               /* In case of U-Boot */ 
      or
       st,eth-ref-clk-sel;               /* In case of Linux Kernel */ 
       snps,axi-config = <&stmmac_axi_config_0>;
       snps,tso;
       power-domains = <&pd_core>;
       status = "disabled";
};

For ecosystem release ≥ v3.1.0

   ethernet0: ethernet@5800a000 {
       compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
       reg = <0x5800a000 0x2000>;
       reg-names = "stmmaceth";
       interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
                             <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
                             <&exti 70 1>;
       interrupt-names = "macirq",
                         "eth_wake_irq",
                         "stm32_pwr_wakeup";
       clock-names = "stmmaceth",
                      "mac-clk-tx",
                      "mac-clk-rx",
                      "eth-ck",
                      "ethstp";
       clocks = <&rcc ETHMAC>,
                      <&rcc ETHTX>,
                      <&rcc ETHRX>,
                      <&rcc ETHCK_K>,
                      <&rcc ETHSTP>;
       st,syscon = <&syscfg 0x4>;
       snps,mixed-burst;
       snps,pbl = <2>;
       snps,en-tx-lpi-clockgating;
       st,ext-phyclk;
       snps,axi-config = <&stmmac_axi_config_0>;
       snps,tso;
       power-domains = <&pd_core>;
       status = "disabled";
};
   &ethernet0 {
       status = "okay";
       pinctrl-0 = <&ethernet0_rmii_pins_a>;
       pinctrl-1 = <&ethernet0_rmii_pins_sleep_a>;
       pinctrl-names = "default", "sleep";
       phy-mode = "rmii";
       max-speed = <100>;
       phy-handle = <&phy0>;
       mdio0 {
               #address-cells = <1>;
               #size-cells = <0>;
               compatible = "snps,dwmac-mdio";
               phy0: ethernet-phy@0 {
                       reg = <0>;
               };
       };
   };

+ update stm32mp15-pinctrl.dtsi to add ETHCK pin in ethernet0_rmii_pins_* node:
For example:

 <STM32_PINMUX('G', 8, AF2)>, /* ETH_RMII_ETHCK */

+ Need also to update TFA to generate 50Mhz 50 MHz clock (from PLL4P or PLL3Q):
for example if PLL4P in ed1 board: update fdts/stm32mp15xx-edx.dtsi

st,pkcs = <
 CLK_CKPER_HSE
 CLK_FMC_ACLK
 CLK_QSPI_ACLK
 - CLK_ETH_DISABLED
 + CLK_ETH_PLL4P
...
 /* VCO = 508.0 MHz => P = 50, Q = 60, R = 60 */
   pll4: st,pll@3 {
     compatible = "st,stm32mp1-pll";
     reg = <3>;
    cfg = < 1 49 11 9 9 PQR(1,1,1) >;
  };

3.3.4 RGMII with Crystal on PHY, CLK125 from PHY (Reference clock (standard RGMII clock name) is provided by a Phy Crystal)[edit]

   &ethernet0 {
       status = "okay";
       pinctrl-0 = <&ethernet0_rgmii_pins_a>;
       pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
       pinctrl-names = "default", "sleep";
       phy-mode = "rgmii";
       max-speed = <1000>;
       phy-handle = <&phy0>;
       mdio0 {
               #address-cells = <1>;
               #size-cells = <0>;
               compatible = "snps,dwmac-mdio";
               phy0: ethernet-phy@0 {
                       reg = <0>;
               };
           };
   };

3.3.5 RGMII with 25MHz 25 MHz on ETH_CLK (no PHY Crystal), CLK125 from PHY (Reference clock (standard RGMII clock name) is provided by a RCC SoC internal clock)[edit]

   &ethernet0 {
       status = "okay";
       pinctrl-0 = <&ethernet0_rgmii_pins_a>;
       pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
       pinctrl-names = "default", "sleep";
       phy-mode = "rgmii";
       max-speed = <1000>;
       phy-handle = <&phy0>;
       mdio0 {
               #address-cells = <1>;
               #size-cells = <0>;
               compatible = "snps,dwmac-mdio";
               phy0: ethernet-phy@0 {
                       reg = <0>;
               };
       };
   };

+ update stm32mp15-pinctrl.dtsi to add ETHCK pin in ethernet0_rgmii_pins_* node:
For example:

 <STM32_PINMUX('G', 8, AF2)>, /* ETH_RGMII_ETHCK */

+ Need also to update TFA to generate 25Mhz 25 MHz clock (from PLL4P or PLL3Q):
for example if PLL4P in ed1 board: update fdts/stm32mp15xx-edx.dtsi

st,pkcs = <
 CLK_CKPER_HSE
 CLK_FMC_ACLK
 CLK_QSPI_ACLK
 - CLK_ETH_DISABLED
 + CLK_ETH_PLL4P
...
 /* VCO = 600.0 MHz => P = 25, Q = 50, R = 50 */
   pll4: st,pll@3 {
     compatible = "st,stm32mp1-pll";
     reg = <3>;
     cfg = < 1 49 23 11 11 PQR(1,1,1) >;
 };

3.3.6 RGMII with Crystal on PHY, no 125Mhz 125MHz from PHY[edit]

For ecosystem release ≤ v3.0.0 only for STM32MP15x lines More info.png

   ethernet0: ethernet@5800a000 {
       compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
       reg = <0x5800a000 0x2000>;
       reg-names = "stmmaceth";
       interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
                             <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
                             <&exti 70 1>;
       interrupt-names = "macirq",
                         "eth_wake_irq",
                         "stm32_pwr_wakeup";
       clock-names = "stmmaceth",
                      "mac-clk-tx",
                      "mac-clk-rx",
                      "eth-ck",
                      "ethstp";
       clocks = <&rcc ETHMAC>,
                      <&rcc ETHTX>,
                      <&rcc ETHRX>,
                      <&rcc ETHCK_K>,
                      <&rcc ETHSTP>;
       st,syscon = <&syscfg 0x4>;
       snps,mixed-burst;
       snps,pbl = <2>;
       snps,en-tx-lpi-clockgating;
       st,eth_clk_sel;               /* In case of U-Boot */ 
      or
       st,eth-clk-sel;               /* In case of Linux Kernel */ 
       snps,axi-config = <&stmmac_axi_config_0>;
       snps,tso;
       power-domains = <&pd_core>;
       status = "disabled";
};

For ecosystem release ≥ v3.1.0

   ethernet0: ethernet@5800a000 {
       compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
       reg = <0x5800a000 0x2000>;
       reg-names = "stmmaceth";
       interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
                             <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
                             <&exti 70 1>;
       interrupt-names = "macirq",
                         "eth_wake_irq",
                         "stm32_pwr_wakeup";
       clock-names = "stmmaceth",
                      "mac-clk-tx",
                      "mac-clk-rx",
                      "eth-ck",
                      "ethstp";
       clocks = <&rcc ETHMAC>,
                      <&rcc ETHTX>,
                      <&rcc ETHRX>,
                      <&rcc ETHCK_K>,
                      <&rcc ETHSTP>;
       st,syscon = <&syscfg 0x4>;
       snps,mixed-burst;
       snps,pbl = <2>;
       snps,en-tx-lpi-clockgating;
       st,ext-phyclk;
       snps,axi-config = <&stmmac_axi_config_0>;
       snps,tso;
       power-domains = <&pd_core>;
       status = "disabled";
};
   &ethernet0 {
       status = "okay";
       pinctrl-0 = <&ethernet0_rgmii_pins_a>;
       pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
       pinctrl-names = "default", "sleep";
       phy-mode = "rgmii";
       max-speed = <1000>;
       phy-handle = <&phy0>;
       mdio0 {
               #address-cells = <1>;
               #size-cells = <0>;
               compatible = "snps,dwmac-mdio";
               phy0: ethernet-phy@0 {
                       reg = <0>;
               };
       };
   };

+ update stm32mp15-pinctrl.dtsi to delete CLK125 pin (also no need of ETHCK pin) in ethernet0_rgmii_pins_* node:

+ Need also to update TFA to generate 125Mhz 125 MHz clock (from PLL4P or PLL3Q):
for example if PLL4P in ed1 board: update fdts/stm32mp15xx-edx.dtsi

st,pkcs = <
 CLK_CKPER_HSE
 CLK_FMC_ACLK
 CLK_QSPI_ACLK
 - CLK_ETH_DISABLED
 + CLK_ETH_PLL4P
...
 /* VCO = 750.0 MHz => P = 125, Q = 62.5, R = 62.5 */
 pll4: st,pll@3 {
     compatible = "st,stm32mp1-pll";
     reg = <3>;
     cfg = < 3 124 5 11 11 PQR(1,1,1) >;
 };

4 How to configure a PHY reset signal[edit]

Some Ethernet PHY have possibility allow the use of GPIO to drive the PHY reset using GPIO .

   &ethernet0 {
       status = "okay";
       pinctrl-0 = <&ethernet0_rgmii_pins_a>;
       pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
       pinctrl-names = "default", "sleep";
       phy-mode = "rgmii";
       max-speed = <1000>;
       phy-handle = <&phy0>;
       mdio0 {
               #address-cells = <1>;
               #size-cells = <0>;
               compatible = "snps,dwmac-mdio";
               phy0: ethernet-phy@0 {
                       compatible = "ethernet-phy-id0007.c131";
                       reset-gpios = <&gpioa 4 GPIO_ACTIVE_LOW | GPIO_PULL_UP>  
                         reset-assert-us = <1000>;
                         reset-deassert-us = <2000>;
                         reg = <0>;
               };
       };
   };

For the kernel update, see "reset-gpios" in Documentation/devicetree/bindings/net/ethernet-phy.yaml[6]


You need to find and replace the value 0007.c131 corresponding to your Ethernet PHY: this can be found in the datasheet of the Ethernet PHY, and find the PHY Identifier 1 and PHY Identifier 2 registers.

For a U-Boot with the same syntax of kernel, except that for "reset-assert-us" and "reset-deassert-us" properties which are not managed (values of this properties are hardcoded in driver (udelay(2)), so you can change these value in function the values can be modified with function: eqos_start_resets_stm32 of file: dwc_eth_qos.c[7]

5 How to enable and use Wake on LAN (WoL) from GMAC[edit]

To perform WoL, Ethernet PHY must have quartz.
From GMAC we can only perform WoL from STOP mode.

To enable wakeup source

 ethtool -s eth0 wol g

To wake up board from host:

  etherwake -i enp0s25 @MAC_Of_TheBoard

6 How to enable and use Wake on LAN (WoL) from PHY[edit]

Under construction.png The feature explained in this section is under construction and will be available only with v4.1.0 ecosystem delivery

Ethernet 1 of STM32MP135x-DK Discovery kit Warning.png has the possibility to use Magic Packet to wake up board from Standby mode.

        eth1: eth1@5800a000 {
            compatible = "snps,dwmac-4.20a", "st,stm32mp13-dwmac";
            reg = <0x5800a000 0x2000>;
            reg-names = "stmmaceth";
            ....
            snps,mixed-burst;
            snps,pbl = <2>;
            snps,axi-config = <&stmmac_axi_config_0>;
            snps,tso;
            '''power-domains = <&pd_core>;''' => to remove to activate WoL from PHY
            '''wakeup-source;'''              => to remove to activate WoL from PHY
            status = "disabled";
         };


    &eth1 {
        status = "okay";
        pinctrl-0 = <&eth1_rmii_pins_a>;
        pinctrl-1 = <&eth1_rmii_sleep_pins_a>;
        pinctrl-names = "default", "sleep";
        phy-mode = "rmii";
        max-speed = <100>;
        phy-handle = <&phy0_eth1>;
        mdio1 {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "snps,dwmac-mdio";
                phy0_eth1: ethernet-phy@0 {
                          compatible = "ethernet-phy-id0007.c131";
                          reset-gpios =  <&mcp23017 9 GPIO_ACTIVE_LOW>;
                          reg = <0>;
                          '''wakeup-source;'''      => to add to activate WoL from PHY
                };
        };
    };

To enable wakeup source

 echo enabled > /sys/devices/platform/soc/5800a000.eth1/mdio_bus/stmmac-0/stmmac-0\:00/power/wakeup

To wake up board from host:

 
 etherwake -i enp0s25 @MAC_Of_TheBoard
6

Furthermore in OPTEE side, we need to configure a wakeup pin in wakeup source.

7 How to configure Ethernet using CubeMX[edit]

The STM32CubeMX tool can be used to configure the STM32MPU device and get the corresponding platform configuration device tree files.
The STM32CubeMX may not support all the properties described in the above DT bindings documentation paragraph. If so, the tool inserts user sections in the generated device tree. These sections can then be edited to add some properties and they are preserved from one generation to another. Refer to STM32CubeMX user manual for further information.

7 8 References[edit]


<noinclude>{{ApplicableFor
|MPUs list=STM32MP13x, STM32MP15x
|MPUs checklist=STM32MP13x,STM32MP15x
}}</noinclude>
{{ReviewsComments|-- [[User:Nathalie Sangouard|Nathalie Sangouard]] ([[User talk:Nathalie Sangouard|talk]]) 16:15, 21 July 2022 (CEST)<br />this article must be reviewed by TW}}== Article purpose ==
This article explains how to configure the [[ETH internal peripheral|Ethernet]] when it is assigned to the Linux<sup>&reg;</sup> OS. In thatthis case, it is controlled by the [[Ethernet overview|Ethernet framework]].

The configuration is performed using the [[Device tree|device tree]] mechanism that. This provides a hardware description of the Ethernet peripheral, used by the STM32 DWMAC driver.

== DT bindings documentation ==
The ''Ethernet'' is a multifunction device.

Each function is represented by a separate binding document:
* "Generic" Ethernet device tree bindings <ref>{{CodeSource | Linux kernel | Documentation/devicetree/bindings/net/snps%2Cdwmac.yaml}}</ref>

* specificSpecific STM32 ETH device tree bindings<ref>{{CodeSource | Linux kernel | Documentation/devicetree/bindings/net/stm32-dwmac.yaml}}</ref>


== DT configuration ==
This hardware description is a combination of the '''STM32 microprocessor''' device tree files (''.dtsi'' extension) and '''board''' device tree files (''.dts'' extension). See the [[Device tree]] for an explanation of the device tree file split. 

=== DT configuration (STM32 level) ===

Ethernet peripheral nodes are located in 
* for {{MicroprocessorDevice | device=13}}  in  stm32mp131.dtsi <ref name="stm32mp131.dtsi">{{CodeSource | Linux kernel | arch/arm/boot/dts/stm32mp131.dtsi | stm32mp131.dtsi}}</ref> file,
* for {{MicroprocessorDevice | device=15}}  in stm32mp151.dtsi <ref name="stm32mp151.dtsi">{{CodeSource | Linux kernel | arch/arm/boot/dts/stm32mp151.dtsi | stm32mp151.dtsi}}</ref> file,
In this file, the status must be set to disabled, and some requiredthe following properties such asmust be set:
* Physical base address and size of the device register map
* STM32 DWMAC interrupts
* stmmaceth clock and Rx, Tx clocks

This is a set of properties that may not vary for a given STM32MP device, such as: register addresses, interrupts, clocks, ...
<pre>

ethernet0: ethernet@5800a000 {
	compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
	reg = <0x5800a000 0x2000>;
	reg-names = "stmmaceth";<&exti 70 IRQ_TYPE_LEVEL_HIGH>;
        interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
        interrupt-names = "macirq",
                          "eth_wake_irq";
	clock-names = "stmmaceth",
		      "mac-clk-tx",
		      "mac-clk-rx",
		      "eth-ck",
		      "ethstp";
	clocks = <&rcc ETHMAC>,<&rcc ETHTX>,<&rcc ETHRX>,<&rcc ETHCK_K>,<&rcc ETHSTP>;
	st,syscon = <&syscfg 0x4>;
	snps,mixed-burst;
	snps,pbl = <2>;
        snps,en-tx-lpi-clockgating;
	snps,axi-config = <&stmmac_axi_config_0>;
	snps,tso;
	power-domains = <&pd_core>;
	status = "disabled";
};</pre>


The required and optional properties are fully described in the [[Ethernet device tree configuration#DT bindings documentation|bindings files]].

{{Warning|This device tree part is related to STM32 microprocessors. It must be kept as is, without being modified by the end-user.}}

=== Ethernet DT configuration (board level) ===

{{Warning|These DT are same between U-Boot and kernel OS}}

The device tree board file (.dts) contains all hardware configurations related to board design. The DT node ('''"ethernet"''') shouldmust be updated to:

* Enable the Ethernet block by setting '''status = "okay".'''
* Configure the pins in use via [[Pinctrl overview|pinctrl]], through '''pinctrl-0''' (default pins), '''pinctrl-1''' (sleep pins) and '''pinctrl-names'''.
* Configure Ethernet interface used '''phy-mode = "rgmii".''', (rmii, mii, gmii).
* Configure Ethernet max speed '''max-speed = <1000>".'''.
<pre>

&ethernet0 {
	status = "okay";
	pinctrl-0 = <&ethernet0_rgmii_pins_a>;
	pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
	pinctrl-names = "default", "sleep";
	phy-mode = "rgmii";
	max-speed = <1000>;
	phy-handle = <&phy0>;

	mdio0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,dwmac-mdio";
		phy0: ethernet-phy@1 {
			reg = <1>;
		};
	};
};</pre>


=== DT configuration examples at board level ===
The example below shows how to configure and enable an Ethernet instance

 &ethernet0 {
    status = "okay";                             {{highlight|/* enable ethernet0 */}} 
    pinctrl-0 = <&ethernet0_rmii_pins_a>;        {{highlight|/* configure pinctrl modes for ethernet0 */}}
    pinctrl-1 = <&ethernet0_rmii_pins_sleep_a>;  {{highlight|/* configure ethernet0_rmii_pins_sleep_a as sleep pinctrl configuration for ethernet0 */}}
    pinctrl-names = "default", "sleep";
    phy-mode = "rmii";                           {{highlight|/* configure ethernet phy mode for ethernet0 */}}
    max-speed = <100>;                           {{highlight|/* configure ethernet max speed for ethernet0 */}}
    phy-handle = <&phy0>;

    mdio0 {
        #address-cells = <1>;
        #size-cells = <0>;
        compatible = "snps,dwmac-mdio";
        phy0: ethernet-phy@1 {
            reg = <1>;                           {{highlight|/* configure ethernet phy @ for ethernet0 */}}
        };
    };
 };

How to configure Ethernet for :
==== RMII with Crystal on PHY (Reference clock (standard RMII clock name) is provided by a Phy Crystal) ====

    &ethernet0 {
        status = "okay";
        pinctrl-0 = <&ethernet0_rmii_pins_a>;
        pinctrl-1 = <&ethernet0_rmii_pins_sleep_a>;
        pinctrl-names = "default", "sleep";
        phy-mode = "rmii";
        max-speed = <100>;
        phy-handle = <&phy0>;
        mdio0 {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "snps,dwmac-mdio";
                phy0: ethernet-phy@0 {
                        reg = <0>;
                };
        };
    };

==== RMII with 25MHz on ETH_CLK (no PHY Crystal), REF_CLK from PHY (Reference clock (standard RMII clock name) is provided by a PHY) ====

    &ethernet0 {
        status = "okay";
        pinctrl-0 = <&ethernet0_rmii_pins_a>;
        pinctrl-1 = <&ethernet0_rmii_pins_sleep_a>;
        pinctrl-names = "default", "sleep";
        phy-mode = "rmii";
        max-speed = <100>;
        phy-handle = <&phy0>;
        mdio0 {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "snps,dwmac-mdio";
                phy0: ethernet-phy@0 {
                        reg = <0>;
                };
        };
    };

+ update stm32mp15-pinctrl.dtsi <ref>{{CodeSource | Linux kernel | arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | arch/arm/boot/dts/stm32mp15-pinctrl.dtsi}}, STM32MP15 pinctrl device tree file</ref> to add ETHCK pin in ethernet0_rmii_pins_* node:<br>

For example:<STM32_PINMUX('G', 8, AF2)>, /* ETH_RMII_ETHCK */

+ Need also to update TFA devicetree to generate 25Mhz clock (from PLL4P or PLL3Q):<br>

for example if PLL4P in ed1 board:
update fdts/stm32mp15xx-edx.dtsi 

 st,pkcs = <
  CLK_CKPER_HSE
  CLK_FMC_ACLK
  CLK_QSPI_ACLK
  '''- CLK_ETH_DISABLED'''
  '''+ CLK_ETH_PLL4P'''
 ...
  /* VCO = 600.0 MHz => P = 25, Q = 50, R = 50 */
    pll4: st,pll@3 {
      compatible = "st,stm32mp1-pll";
      reg = <3>;
      '''cfg = < 1 49 23 11 11 PQR(1,1,1) >;'''
  };

==== RMII with 50MHz on ETH_CLK (no PHY Crystal), internal REF_CLK from RCC  (Reference clock (standard RMII clock name) is provided by aan RCC SoC internal clock) ====

For {{EcosystemRelease | revision=3.0.0 | range=and before}} , only for {{MicroprocessorDevice | device=15}}

    ethernet0: ethernet@5800a000 {
        compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
        reg = <0x5800a000 0x2000>;
        reg-names = "stmmaceth";
        interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,<&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,<&exti 70 1>;
        interrupt-names = "macirq",
                          "eth_wake_irq",
                          "stm32_pwr_wakeup";
        clock-names = "stmmaceth",
                       "mac-clk-tx",
                       "mac-clk-rx",
                       "eth-ck",
                       "ethstp";
        clocks = <&rcc ETHMAC>,<&rcc ETHTX>,<&rcc ETHRX>,<&rcc ETHCK_K>,<&rcc ETHSTP>;
        st,syscon = <&syscfg 0x4>;
        snps,mixed-burst;
        snps,pbl = <2>;
        snps,en-tx-lpi-clockgating;
        '''st,eth_ref_clk_sel;'''               {{highlight|/* In case of U-Boot */}} 
       or
        '''st,eth-ref-clk-sel;'''               {{highlight|/* In case of Linux Kernel */}} 
        snps,axi-config = <&stmmac_axi_config_0>;
        snps,tso;
        power-domains = <&pd_core>;
        status = "disabled";
 };

For {{EcosystemRelease | revision=3.1.0 | range=and after}}

    ethernet0: ethernet@5800a000 {
        compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
        reg = <0x5800a000 0x2000>;
        reg-names = "stmmaceth";
        interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,<&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,<&exti 70 1>;
        interrupt-names = "macirq",
                          "eth_wake_irq",
                          "stm32_pwr_wakeup";
        clock-names = "stmmaceth",
                       "mac-clk-tx",
                       "mac-clk-rx",
                       "eth-ck",
                       "ethstp";
        clocks = <&rcc ETHMAC>,<&rcc ETHTX>,<&rcc ETHRX>,<&rcc ETHCK_K>,<&rcc ETHSTP>;
        st,syscon = <&syscfg 0x4>;
        snps,mixed-burst;
        snps,pbl = <2>;
        snps,en-tx-lpi-clockgating;
        '''st,ext-phyclk;'''
        snps,axi-config = <&stmmac_axi_config_0>;
        snps,tso;
        power-domains = <&pd_core>;
        status = "disabled";
 };

    &ethernet0 {
        status = "okay";
        pinctrl-0 = <&ethernet0_rmii_pins_a>;
        pinctrl-1 = <&ethernet0_rmii_pins_sleep_a>;
        pinctrl-names = "default", "sleep";
        phy-mode = "rmii";
        max-speed = <100>;
        phy-handle = <&phy0>;
        mdio0 {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "snps,dwmac-mdio";
                phy0: ethernet-phy@0 {
                        reg = <0>;
                };
        };
    };

+ update stm32mp15-pinctrl.dtsi to add ETHCK pin in ethernet0_rmii_pins_* node:<br>

For example:<STM32_PINMUX('G', 8, AF2)>, /* ETH_RMII_ETHCK */

+ Need also to update TFA to generate 50Mhz 50 MHz clock (from PLL4P or PLL3Q):<br>

for example if PLL4P in ed1 board:
update fdts/stm32mp15xx-edx.dtsi 
 st,pkcs = <
  CLK_CKPER_HSE
  CLK_FMC_ACLK
  CLK_QSPI_ACLK
  '''- CLK_ETH_DISABLED'''
  '''+ CLK_ETH_PLL4P'''
 ...
  /* VCO = 508.0 MHz => P = 50, Q = 60, R = 60 */
    pll4: st,pll@3 {
      compatible = "st,stm32mp1-pll";
      reg = <3>;
     '''cfg = < 1 49 11 9 9 PQR(1,1,1) >;'''
   };

==== RGMII with Crystal on PHY, CLK125 from PHY (Reference clock (standard RGMII clock name) is provided by a Phy Crystal) ====

    &ethernet0 {
        status = "okay";
        pinctrl-0 = <&ethernet0_rgmii_pins_a>;
        pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
        pinctrl-names = "default", "sleep";
        phy-mode = "rgmii";
        max-speed = <1000>;
        phy-handle = <&phy0>;
        mdio0 {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "snps,dwmac-mdio";
                phy0: ethernet-phy@0 {
                        reg = <0>;
                };
            };
    };

==== RGMII with 25MHz 25 MHz on ETH_CLK (no PHY Crystal), CLK125 from PHY (Reference clock (standard RGMII clock name) is provided by a RCC SoC internal clock) ====

    &ethernet0 {
        status = "okay";
        pinctrl-0 = <&ethernet0_rgmii_pins_a>;
        pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
        pinctrl-names = "default", "sleep";
        phy-mode = "rgmii";
        max-speed = <1000>;
        phy-handle = <&phy0>;
        mdio0 {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "snps,dwmac-mdio";
                phy0: ethernet-phy@0 {
                        reg = <0>;
                };
        };
    };

+ update stm32mp15-pinctrl.dtsi to add ETHCK pin in ethernet0_rgmii_pins_* node:<br>

For example:<STM32_PINMUX('G', 8, AF2)>, /* ETH_RGMII_ETHCK */

+ Need also to update TFA to generate 25Mhz 25 MHz clock (from PLL4P or PLL3Q):<br>

for example if PLL4P in ed1 board:
update fdts/stm32mp15xx-edx.dtsi  
 st,pkcs = <
  CLK_CKPER_HSE
  CLK_FMC_ACLK
  CLK_QSPI_ACLK
  '''- CLK_ETH_DISABLED'''
  '''+ CLK_ETH_PLL4P'''
 ...
  /* VCO = 600.0 MHz => P = 25, Q = 50, R = 50 */
    pll4: st,pll@3 {
      compatible = "st,stm32mp1-pll";
      reg = <3>;
      '''cfg = < 1 49 23 11 11 PQR(1,1,1) >;'''
  };

==== RGMII with Crystal on PHY, no 125Mhz125MHz from PHY ====

For {{EcosystemRelease | revision=3.0.0 | range=and before}} only for {{MicroprocessorDevice | device=15}}

    ethernet0: ethernet@5800a000 {
        compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
        reg = <0x5800a000 0x2000>;
        reg-names = "stmmaceth";
        interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,<&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,<&exti 70 1>;
        interrupt-names = "macirq",
                          "eth_wake_irq",
                          "stm32_pwr_wakeup";
        clock-names = "stmmaceth",
                       "mac-clk-tx",
                       "mac-clk-rx",
                       "eth-ck",
                       "ethstp";
        clocks = <&rcc ETHMAC>,<&rcc ETHTX>,<&rcc ETHRX>,<&rcc ETHCK_K>,<&rcc ETHSTP>;
        st,syscon = <&syscfg 0x4>;
        snps,mixed-burst;
        snps,pbl = <2>;
        snps,en-tx-lpi-clockgating;
        '''st,eth_clk_sel;'''               {{highlight|/* In case of U-Boot */}} 
       or
        '''st,eth-clk-sel;'''               {{highlight|/* In case of Linux Kernel */}} 
        snps,axi-config = <&stmmac_axi_config_0>;
        snps,tso;
        power-domains = <&pd_core>;
        status = "disabled";
 };

For {{EcosystemRelease | revision=3.1.0 | range=and after}}

    ethernet0: ethernet@5800a000 {
        compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
        reg = <0x5800a000 0x2000>;
        reg-names = "stmmaceth";
        interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,<&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,<&exti 70 1>;
        interrupt-names = "macirq",
                          "eth_wake_irq",
                          "stm32_pwr_wakeup";
        clock-names = "stmmaceth",
                       "mac-clk-tx",
                       "mac-clk-rx",
                       "eth-ck",
                       "ethstp";
        clocks = <&rcc ETHMAC>,<&rcc ETHTX>,<&rcc ETHRX>,<&rcc ETHCK_K>,<&rcc ETHSTP>;
        st,syscon = <&syscfg 0x4>;
        snps,mixed-burst;
        snps,pbl = <2>;
        snps,en-tx-lpi-clockgating;
        '''st,ext-phyclk;'''
        snps,axi-config = <&stmmac_axi_config_0>;
        snps,tso;
        power-domains = <&pd_core>;
        status = "disabled";
 };

    &ethernet0 {
        status = "okay";
        pinctrl-0 = <&ethernet0_rgmii_pins_a>;
        pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
        pinctrl-names = "default", "sleep";
        phy-mode = "rgmii";
        max-speed = <1000>;
        phy-handle = <&phy0>;
        mdio0 {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "snps,dwmac-mdio";
                phy0: ethernet-phy@0 {
                        reg = <0>;
                };
        };
    };

+ update stm32mp15-pinctrl.dtsi to delete CLK125 pin (also no need of ETHCK pin) in ethernet0_rgmii_pins_* node:<br>


+ Need also to update TFA to generate 125Mhz 125 MHz clock (from PLL4P or PLL3Q):<br>

for example if PLL4P in ed1 board:
update fdts/stm32mp15xx-edx.dtsi 
 st,pkcs = <
  CLK_CKPER_HSE
  CLK_FMC_ACLK
  CLK_QSPI_ACLK
  '''- CLK_ETH_DISABLED'''
  '''+ CLK_ETH_PLL4P'''
 ...
  /* VCO = 750.0 MHz => P = 125, Q = 62.5, R = 62.5 */
  pll4: st,pll@3 {
      compatible = "st,stm32mp1-pll";
      reg = <3>;
      '''cfg = < 3 124 5 11 11 PQR(1,1,1) >;'''
  };

== How to configure a PHY reset signal ==
Some Ethernet PHY have possibility to drive PHY reset using GPIO
allow the use of GPIO to drive the PHY reset.
&ethernet0 {
        status = "okay";
        pinctrl-0 = <&ethernet0_rgmii_pins_a>;
        pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
        pinctrl-names = "default", "sleep";
        phy-mode = "rgmii";
        max-speed = <1000>;
        phy-handle = <&phy0>;
        mdio0 {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "snps,dwmac-mdio";
                phy0: ethernet-phy@0 {
                        '''compatible = "ethernet-phy-id0007.c131";'''
                        '''reset-gpios = <&gpioa 4 GPIO_ACTIVE_LOW | GPIO_PULL_UP>'''  
                          reset-assert-us = <1000>;
                          reset-deassert-us = <2000>;
                          reg = <0>;
                };
        };
    };

For the kernel update, see "reset-gpios" in Documentation/devicetree/bindings/net/ethernet-phy.yaml<ref>https://www.kernel.org/doc/Documentation/devicetree/bindings/net/ethernet-phy.yaml, More information</ref> <br>


You need to find and replace the value '''0007.c131''' corresponding to your Ethernet PHY: this can be found in the datasheet of the Ethernet PHY, and find the '''PHY Identifier 1''' and '''PHY Identifier 2''' registers.

For a U-Boot with the same syntax of kernel, except thatfor "reset-assert-us" and "reset-deassert-us" properties which are not managed (values of this properties are hardcoded in driver (udelay(2)), so youthe values can change these value in functionbe modified with function: eqos_start_resets_stm32 of file: dwc_eth_qos.c<ref>https://github.com/u-boot/u-boot/blob/master/drivers/net/dwc_eth_qos.c, More information</ref>



{{ReviewsComments|-- [[User:Emmanuel Combette|Emmanuel Combette]] ([[User talk:Emmanuel Combette|talk]]) 12:04, 21 July 2022 (CEST)<br />Could we add the case where Magic Packet are detected by ETH_GMAC, explaining also that we can only go to Stop in this case instead of Stanby with WoL done by ETH_PHY ? }}
== How to enable and use Wake on LAN (WoL) from GMAC ==

To perform WoL, Ethernet PHY must have quartz.<br>

From GMAC we can only perform WoL from STOP mode.

To enable wakeup source<br>

  ethtool -s eth0 wol g

To wake up board from host:
  {{PC$}} etherwake -i enp0s25 @MAC_Of_TheBoard
== How to enable and use Wake on LAN (WoL) from PHY ==
{{UnderConstruction|'''The feature explained in this section is under construction and will be available only with v4.1.0 ecosystem delivery'''
Ethernet 1 of {{Board | type=135x-DK}} has the  possibility to use Magic Packet to wake up board from Standby mode.<pre>

        eth1: eth1@5800a000 {
            compatible = "snps,dwmac-4.20a", "st,stm32mp13-dwmac";
            reg = <0x5800a000 0x2000>;
            reg-names = "stmmaceth";
            ....
            snps,mixed-burst;
            snps,pbl = <2>;
            snps,axi-config = <&stmmac_axi_config_0>;
            snps,tso;
            '''power-domains = <&pd_core>;''' => to remove to activate WoL from PHY
            '''wakeup-source;'''              => to remove to activate WoL from PHY
            status = "disabled";
         };

    &eth1 {
        status = "okay";
        pinctrl-0 = <&eth1_rmii_pins_a>;
        pinctrl-1 = <&eth1_rmii_sleep_pins_a>;
        pinctrl-names = "default", "sleep";
        phy-mode = "rmii";
        max-speed = <100>;
        phy-handle = <&phy0_eth1>;
        mdio1 {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "snps,dwmac-mdio";
                phy0_eth1: ethernet-phy@0 {
                          compatible = "ethernet-phy-id0007.c131";
                          reset-gpios =  <&mcp23017 9 GPIO_ACTIVE_LOW>;
                          reg = <0>;
                          '''wakeup-source;'''      => to add to activate WoL from PHY
                };
        };
    };</pre>

To enable wakeup source<br>

  echo enabled > /sys/devices/platform/soc/5800a000.eth1/mdio_bus/stmmac-0/stmmac-0\:00/power/wakeup

To wake up board from host:
  {{PC$}} etherwake -i enp0s25 @MAC_Of_TheBoard

Furthermore in OPTEE side, we need to configure a wakeup pin in wakeup source.}}

== How to configure Ethernet using CubeMX ==
The [[STM32CubeMX]] tool can be used to configure the STM32MPU device and get the corresponding [[Device_tree#STM32|platform configuration device tree]] files.<br />

The STM32CubeMX may not support all the properties described in the above [[#DT bindings documentation|DT bindings documentation]] paragraph. If so, the tool inserts '''user sections''' in the generated device tree. These sections can then be edited to add some properties and they are preserved from one generation to another. Refer to [[STM32CubeMX]] user manual for further information.

==References==<references />

<noinclude>

[[Category:Device tree configuration]]
[[Category:Ethernet]]
{{PublicationRequestId | 10170 | 2019-01-02 |24110 | 2022-07-27 | 10170 - 2019-01-02  BrunoB}}
{{ArticleBasedOnModel | Peripheral or framework device tree configuration model}}</noinclude>
(16 intermediate revisions by 5 users not shown)
Line 3: Line 3:
 
|MPUs checklist=STM32MP13x,STM32MP15x
 
|MPUs checklist=STM32MP13x,STM32MP15x
 
}}</noinclude>
 
}}</noinclude>
  +
{{ReviewsComments|-- [[User:Nathalie Sangouard|Nathalie Sangouard]] ([[User talk:Nathalie Sangouard|talk]]) 16:15, 21 July 2022 (CEST)<br />this article must be reviewed by TW}}
 
== Article purpose ==
 
== Article purpose ==
This article explains how to configure the [[ETH internal peripheral|Ethernet]] when it is assigned to the Linux<sup>&reg;</sup> OS. In that case, it is controlled by the [[Ethernet overview|Ethernet framework]].
+
This article explains how to configure the [[ETH internal peripheral|Ethernet]] when it is assigned to the Linux<sup>&reg;</sup> OS. In this case, it is controlled by the [[Ethernet overview|Ethernet framework]].
   
The configuration is performed using the [[Device tree|device tree]] mechanism that provides a hardware description of the Ethernet peripheral, used by the STM32 DWMAC driver.
+
The configuration is performed using the [[Device tree|device tree]] mechanism. This provides a hardware description of the Ethernet peripheral used by the STM32 DWMAC driver.
   
 
== DT bindings documentation ==
 
== DT bindings documentation ==
Line 13: Line 14:
 
Each function is represented by a separate binding document:
 
Each function is represented by a separate binding document:
 
* "Generic" Ethernet device tree bindings <ref>{{CodeSource | Linux kernel | Documentation/devicetree/bindings/net/snps%2Cdwmac.yaml}}</ref>
 
* "Generic" Ethernet device tree bindings <ref>{{CodeSource | Linux kernel | Documentation/devicetree/bindings/net/snps%2Cdwmac.yaml}}</ref>
* specific STM32 ETH device tree bindings<ref>{{CodeSource | Linux kernel | Documentation/devicetree/bindings/net/stm32-dwmac.yaml}}</ref>
+
* Specific STM32 ETH device tree bindings<ref>{{CodeSource | Linux kernel | Documentation/devicetree/bindings/net/stm32-dwmac.yaml}}</ref>
   
 
== DT configuration ==
 
== DT configuration ==
Line 23: Line 24:
 
* for {{MicroprocessorDevice | device=13}}  in  stm32mp131.dtsi <ref name="stm32mp131.dtsi">{{CodeSource | Linux kernel | arch/arm/boot/dts/stm32mp131.dtsi | stm32mp131.dtsi}}</ref> file,
 
* for {{MicroprocessorDevice | device=13}}  in  stm32mp131.dtsi <ref name="stm32mp131.dtsi">{{CodeSource | Linux kernel | arch/arm/boot/dts/stm32mp131.dtsi | stm32mp131.dtsi}}</ref> file,
 
* for {{MicroprocessorDevice | device=15}}  in stm32mp151.dtsi <ref name="stm32mp151.dtsi">{{CodeSource | Linux kernel | arch/arm/boot/dts/stm32mp151.dtsi | stm32mp151.dtsi}}</ref> file,
 
* for {{MicroprocessorDevice | device=15}}  in stm32mp151.dtsi <ref name="stm32mp151.dtsi">{{CodeSource | Linux kernel | arch/arm/boot/dts/stm32mp151.dtsi | stm32mp151.dtsi}}</ref> file,
In this file, the status must be set to disabled and some required properties such as:
+
In this file, the status must be set to disabled, and the following properties must be set:
 
* Physical base address and size of the device register map
 
* Physical base address and size of the device register map
 
* STM32 DWMAC interrupts
 
* STM32 DWMAC interrupts
Line 68: Line 69:
 
{{Warning|These DT are same between U-Boot and kernel OS}}
 
{{Warning|These DT are same between U-Boot and kernel OS}}
   
The device tree board file (.dts) contains all hardware configurations related to board design. The DT node ('''"ethernet"''') should be updated to:
+
The device tree board file (.dts) contains all hardware configurations related to board design. The DT node ('''"ethernet"''') must be updated to:
   
 
* Enable the Ethernet block by setting '''status = "okay".'''
 
* Enable the Ethernet block by setting '''status = "okay".'''
Line 181: Line 182:
 
   };
 
   };
   
==== RMII with 50MHz on ETH_CLK (no PHY Crystal), internal REF_CLK from RCC  (Reference clock (standard RMII clock name) is provided by a RCC SoC internal clock) ====
+
==== RMII with 50MHz on ETH_CLK (no PHY Crystal), internal REF_CLK from RCC  (Reference clock (standard RMII clock name) is provided by an RCC SoC internal clock) ====
   
 
For {{EcosystemRelease | revision=3.0.0 | range=and before}} , only for {{MicroprocessorDevice | device=15}}
 
For {{EcosystemRelease | revision=3.0.0 | range=and before}} , only for {{MicroprocessorDevice | device=15}}
Line 273: Line 274:
 
   <STM32_PINMUX('G', 8, AF2)>, /* ETH_RMII_ETHCK */
 
   <STM32_PINMUX('G', 8, AF2)>, /* ETH_RMII_ETHCK */
   
+ Need also to update TFA to generate 50Mhz clock (from PLL4P or PLL3Q):<br>
+
+ Need also to update TFA to generate 50 MHz clock (from PLL4P or PLL3Q):<br>
 
for example if PLL4P in ed1 board:
 
for example if PLL4P in ed1 board:
 
update fdts/stm32mp15xx-edx.dtsi  
 
update fdts/stm32mp15xx-edx.dtsi  
Line 310: Line 311:
 
     };
 
     };
   
==== RGMII with 25MHz on ETH_CLK (no PHY Crystal), CLK125 from PHY (Reference clock (standard RGMII clock name) is provided by a RCC SoC internal clock) ====
+
==== RGMII with 25 MHz on ETH_CLK (no PHY Crystal), CLK125 from PHY (Reference clock (standard RGMII clock name) is provided by a RCC SoC internal clock) ====
   
 
     &ethernet0 {
 
     &ethernet0 {
Line 334: Line 335:
 
   <STM32_PINMUX('G', 8, AF2)>, /* ETH_RGMII_ETHCK */
 
   <STM32_PINMUX('G', 8, AF2)>, /* ETH_RGMII_ETHCK */
   
+ Need also to update TFA to generate 25Mhz clock (from PLL4P or PLL3Q):<br>
+
+ Need also to update TFA to generate 25 MHz clock (from PLL4P or PLL3Q):<br>
 
for example if PLL4P in ed1 board:
 
for example if PLL4P in ed1 board:
 
update fdts/stm32mp15xx-edx.dtsi   
 
update fdts/stm32mp15xx-edx.dtsi   
Line 351: Line 352:
 
   };
 
   };
   
==== RGMII with Crystal on PHY, no 125Mhz from PHY ====
+
==== RGMII with Crystal on PHY, no 125MHz from PHY ====
   
 
For {{EcosystemRelease | revision=3.0.0 | range=and before}} only for {{MicroprocessorDevice | device=15}}
 
For {{EcosystemRelease | revision=3.0.0 | range=and before}} only for {{MicroprocessorDevice | device=15}}
Line 441: Line 442:
 
+ update stm32mp15-pinctrl.dtsi to delete CLK125 pin (also no need of ETHCK pin) in ethernet0_rgmii_pins_* node:<br>
 
+ update stm32mp15-pinctrl.dtsi to delete CLK125 pin (also no need of ETHCK pin) in ethernet0_rgmii_pins_* node:<br>
   
+ Need also to update TFA to generate 125Mhz clock (from PLL4P or PLL3Q):<br>
+
+ Need also to update TFA to generate 125 MHz clock (from PLL4P or PLL3Q):<br>
 
for example if PLL4P in ed1 board:
 
for example if PLL4P in ed1 board:
 
update fdts/stm32mp15xx-edx.dtsi  
 
update fdts/stm32mp15xx-edx.dtsi  
Line 459: Line 460:
   
 
== How to configure a PHY reset signal ==
 
== How to configure a PHY reset signal ==
Some Ethernet PHY have possibility to drive PHY reset using GPIO
+
Some Ethernet PHY allow the use of GPIO to drive the PHY reset.
   
 
     &ethernet0 {
 
     &ethernet0 {
Line 483: Line 484:
 
     };
 
     };
   
For kernel update see "reset-gpios" in Documentation/devicetree/bindings/net/ethernet-phy.yaml<ref>https://www.kernel.org/doc/Documentation/devicetree/bindings/net/ethernet-phy.yaml, More information</ref> <br>
+
For the kernel update, see "reset-gpios" in Documentation/devicetree/bindings/net/ethernet-phy.yaml<ref>https://www.kernel.org/doc/Documentation/devicetree/bindings/net/ethernet-phy.yaml, More information</ref> <br>
 
                  
 
                  
   
You need to find and replace value '''0007.c131''' corresponding to your Ethernet PHY: this can be found in datasheet of the Ethernet PHY, and find '''PHY Identifier 1''' and '''PHY Identifier 2''' registers.
+
You need to find and replace the value '''0007.c131''' corresponding to your Ethernet PHY: this can be found in the datasheet of the Ethernet PHY, and find the '''PHY Identifier 1''' and '''PHY Identifier 2''' registers.
   
For U-Boot same syntax of kernel, except that "reset-assert-us" and "reset-deassert-us" properties which are not managed (values of this properties are hardcoded in driver (udelay(2)), so you can change these value in function eqos_start_resets_stm32 of file dwc_eth_qos.c<ref>https://github.com/u-boot/u-boot/blob/master/drivers/net/dwc_eth_qos.c, More information</ref>  
+
For a U-Boot with the same syntax of kernel, except for "reset-assert-us" and "reset-deassert-us" properties which are not managed (values of this properties are hardcoded in driver (udelay(2)), the values can be modified with function: eqos_start_resets_stm32 of file: dwc_eth_qos.c<ref>https://github.com/u-boot/u-boot/blob/master/drivers/net/dwc_eth_qos.c, More information</ref>
   
{{ReviewsComments|-- [[User:Emmanuel Combette|Emmanuel Combette]] ([[User talk:Emmanuel Combette|talk]]) 12:04, 21 July 2022 (CEST)<br />Could we add the case where Magic Packet are detected by ETH_GMAC, explaining also that we can only go to Stop in this case instead of Stanby with WoL done by ETH_PHY ? }}
+
== How to enable and use Wake on LAN (WoL) from GMAC ==
  +
 
  +
To perform WoL, Ethernet PHY must have quartz.<br>
  +
From GMAC we can only perform WoL from STOP mode.
  +
 
  +
To enable wakeup source<br>
  +
  ethtool -s eth0 wol g
  +
 
  +
To wake up board from host:
  +
  {{PC$}} etherwake -i enp0s25 @MAC_Of_TheBoard
   
 
== How to enable and use Wake on LAN (WoL) from PHY ==
 
== How to enable and use Wake on LAN (WoL) from PHY ==
Line 537: Line 547:
 
To wake up board from host:
 
To wake up board from host:
 
   {{PC$}} etherwake -i enp0s25 @MAC_Of_TheBoard
 
   {{PC$}} etherwake -i enp0s25 @MAC_Of_TheBoard
  +
  +
Furthermore in OPTEE side, we need to configure a wakeup pin in wakeup source.
 
}}
 
}}
   
Line 549: Line 561:
 
[[Category:Device tree configuration]]
 
[[Category:Device tree configuration]]
 
[[Category:Ethernet]]
 
[[Category:Ethernet]]
{{PublicationRequestId | 10170 | 2019-01-02 | BrunoB}}
+
{{PublicationRequestId |24110 | 2022-07-27 | 10170 - 2019-01-02 BrunoB}}
 
{{ArticleBasedOnModel | Peripheral or framework device tree configuration model}}
 
{{ArticleBasedOnModel | Peripheral or framework device tree configuration model}}
 
</noinclude>
 
</noinclude>