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Difference between revisions of "DMA internal peripheral"
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Contents
1 Article purpose[edit]
The purpose of this article is to:
- briefly introduce the DMA peripheral and its main features
- indicate the level of security supported by this hardware block
- explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
- explain, when necessary, how to configure the DMA peripheral.
2 Peripheral overview[edit]
The DMA peripheral is used to perform direct accesses from/to a device or a memory. Each DMA instance supports 8 channels. The selection of the device connected to each DMA channel and controlling the DMA transfers is done via the DMAMUX.
Note: Directly accessing DDR from the DMA is not recommended for high-bandwith or latency-critical transfers. This means that DMA transfers configured by the Arm® Cortex®-A7 operating system, that usually target buffers in external memory, require a hardware mechanism to chain the DMA and a MDMA channel in order to achieve the following flow:
- DDR<-> MDMA <-> MCU SRAM <-> DMA <-> device
This feature was already present on STM32H7 microcontroller Series. It is documented in application note AN5001[1].
2.1 Features[edit]
Refer to the STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to see which features are implemented.
2.2 Security support[edit]
The DMA is a non-secure peripheral.
3 Peripheral usage and associated software[edit]
3.1 Boot time[edit]
The DMA is not used at boot time.
3.2 Runtime[edit]
3.2.1 Overview[edit]
Each DMA instances instance can be allocated to:
- the Arm® Cortex®-A7 non-secure core to be controlled in Linux® by the dmaengine framework
or
- the Arm® Cortex®-M4 to be controlled in STM32Cube MPU Package by the DMA HAL driver
3.2.2 Software frameworks[edit]
Internal peripherals software table template
| Core/DMA | DMA | | Linux dmaengine framework | STM32Cube DMA driver | |- |}
3.2.3 Peripheral configuration[edit]
The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the STM32CubeMX tool for all internal peripherals, and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article.
3.2.4 Peripheral assignment[edit]
Internal peripherals assignment table template
| rowspan="2" | Core/DMA | rowspan="2" | DMA | DMA1 | | ☐ | ☐ | Assignment (single choice) |- | DMA2 | | ☐ | ☐ | Assignment (single choice) |-
|}
4 References[edit]
<noinclude> {{ClonedFrom | stm32mpu}}</noinclude> ==Article purpose== The purpose of this article is to: * briefly introduce the DMA peripheral and its main features * indicate the level of security supported by this hardware block * explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components * explain, when necessary, how to configure the DMA peripheral. ==Peripheral overview== The '''DMA''' peripheral is used to perform direct accesses from/to a device or a memory. Each DMA instance supports 8 channels. The selection of the device connected to each DMA channel and controlling the DMA transfers is done via the [[DMAMUX internal peripheral|DMAMUX]].<br /><br /> Note: Directly accessing [[DDRCTRL and DDRPHYC internal peripherals|DDR]] from the DMA is not recommended for high-bandwith or latency-critical transfers. This means that DMA transfers configured by the Arm<sup>®</sup> Cortex<sup>®</sup>-A7 operating system, that usually target buffers in external memory, require a hardware mechanism to chain the DMA and a [[MDMA internal peripheral|MDMA]] channel in order to achieve the following flow:<br /> {{ReviewsComments|LPA W905.5 typo ? that usually target buffers in [[MCU SRAM internal memory|MCU SRAM]], as initiator is Linux kernel here, you want to say "that usually traget buffers in external memory ? }}:DDR<-> MDMA <-> MCU SRAM <-> DMA <-> device <br /> This feature was already present on STM32H7 microcontroller Series. It is documented in application note AN5001<ref>http://www.st.com/resource/en/application_note/dm00360392.pdf</ref>. ===Features=== Refer to the [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software components, introduced below, to see which features are implemented. ===Security support=== The DMA is a '''non-secure''' peripheral. ==Peripheral usage and associated software== ===Boot time=== The DMA is not used at boot time. ===Runtime=== ====Overview==== Each DMA instancesinstance can be allocated to:{{ReviewsComments| LPA W905.5: Each DMA instance ?}}* the Arm<sup>®</sup> Cortex<sup>®</sup>-A7 non-secure core to be controlled in Linux<sup>®</sup> by the [[Dmaengine overview|dmaengine]] framework or * the Arm<sup>®</sup> Cortex<sup>®</sup>-M4 to be controlled in STM32Cube MPU Package by the [[STM32CubeMP1 architecture|DMA HAL driver]] ====Software frameworks==== {{:Internal_peripherals_software_table_template}} | Core/DMA | [[DMA internal peripheral|DMA]] | | [[Dmaengine overview|Linux dmaengine framework]] | [[STM32CubeMP1 architecture|STM32Cube DMA driver]] | |- |} ====Peripheral configuration==== The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the [[STM32CubeMX]] tool for all internal peripherals, and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article. ====Peripheral assignment==== {{:Internal_peripherals_assignment_table_template}}<onlyinclude> | rowspan="2" | Core/DMA | rowspan="2" | [[DMA internal peripheral|DMA]] | DMA1 | | <span title="assignable peripheral" style="font-size:21px">☐</span> | <span title="assignable peripheral" style="font-size:21px">☐</span> | Assignment (single choice) |- | DMA2 | | <span title="assignable peripheral" style="font-size:21px">☐</span> | <span title="assignable peripheral" style="font-size:21px">☐</span> | Assignment (single choice) |-</onlyinclude> |} ==References==<references/> <noinclude> [[Category:DMA peripherals]] {{PublicationRequestId | 9109 | 2018-10-10 | AnneJ}} {{ArticleBasedOnModel| Internal peripheral article model}}</noinclude>
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==Article purpose== |
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Note: Directly accessing [[DDRCTRL and DDRPHYC internal peripherals|DDR]] from the DMA is not recommended for high-bandwith or latency-critical transfers. This means that DMA transfers configured by the Arm<sup>®</sup> Cortex<sup>®</sup>-A7 operating system, that usually target buffers in external memory, require a hardware mechanism to chain the DMA and a [[MDMA internal peripheral|MDMA]] channel in order to achieve the following flow:<br /> |
Note: Directly accessing [[DDRCTRL and DDRPHYC internal peripherals|DDR]] from the DMA is not recommended for high-bandwith or latency-critical transfers. This means that DMA transfers configured by the Arm<sup>®</sup> Cortex<sup>®</sup>-A7 operating system, that usually target buffers in external memory, require a hardware mechanism to chain the DMA and a [[MDMA internal peripheral|MDMA]] channel in order to achieve the following flow:<br /> |
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:DDR<-> MDMA <-> MCU SRAM <-> DMA <-> device <br /> |
:DDR<-> MDMA <-> MCU SRAM <-> DMA <-> device <br /> |
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This feature was already present on STM32H7 microcontroller Series. It is documented in application note AN5001<ref>http://www.st.com/resource/en/application_note/dm00360392.pdf</ref>. |
This feature was already present on STM32H7 microcontroller Series. It is documented in application note AN5001<ref>http://www.st.com/resource/en/application_note/dm00360392.pdf</ref>. |
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===Runtime=== |
===Runtime=== |
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====Overview==== |
====Overview==== |
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| − | Each DMA |
+ | Each DMA instance can be allocated to: |
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* the Arm<sup>®</sup> Cortex<sup>®</sup>-A7 non-secure core to be controlled in Linux<sup>®</sup> by the [[Dmaengine overview|dmaengine]] framework |
* the Arm<sup>®</sup> Cortex<sup>®</sup>-A7 non-secure core to be controlled in Linux<sup>®</sup> by the [[Dmaengine overview|dmaengine]] framework |
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