DDRCTRL and DDRPHYC device tree configuration

Revision as of 13:57, 26 November 2021 by Nicolas Le Bayon (talk | contribs) (DT configuration (STM32 level))
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)
Applicable for STM32MP13x lines, STM32MP15x lines

1 Article purpose[edit]

This article explains how to configure the DDRCTRL and DDRPHYC internal peripherals from the first stage bootloader.

The configuration is performed using the device tree mechanism that provides a hardware description of the DDR subsystem (DDR controler and DDR PHY peripheral), and embeds the configuration used by the first stage bootloader to initialize the DDR before loading the second stage bootloader.

The DDR settings are only used in the device tree of the boot chain FSBL, that is, in the TF-A device tree for OpenSTLinux official delivery (or in SPL only for the DDR tuning tool).

2 DT bindings documentation[edit]

The DDR subsystem is a 'memory-controller' device represented by the device tree bindings documented below:

  • TF-A: docs/devicetree/bindings/memory-controllers/st,stm32mp1-ddr.txt"[1]
  • U-Boot: doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt"[2]

3 DT configuration[edit]

This hardware description is a combination of the STM32 microprocessor device tree files (.dtsi extension) and board device tree files (.dts extension). See the Device tree for an explanation of the device-tree file split.

STM32CubeMX can be used to generate this DDR board device tree. Refer to How to configure the DT using STM32CubeMX for more details.

3.1 DT configuration (STM32 level)[edit]

The STM32MP1 DDR node is located

  • for STM32MP13x lines Warning.png in stm32mp131.dtsi [3]
  • for STM32MP15x lines More info.png in stm32mp151.dtsi [4]

see Device tree for further explanation.

Warning white.png Warning
This device tree part is related to STM32 microprocessors. It must be kept as is, without being modified by the end user.

For example:

 1  		ddr: ddr@5a003000{
 2  			compatible = "st,stm32mp1-ddr";
 3  			reg = <0x5A003000 0x550 0x5A004000 0x234>;
 4  			clocks = <&rcc AXIDCG>,
 5  				 <&rcc DDRC1>,
 6  				 <&rcc DDRC2>,
 7  				 <&rcc DDRPHYC>,
 8  				 <&rcc DDRCAPB>,
 9  				 <&rcc DDRPHYCAPB>;
10  			clock-names = "axidcg",
11  				      "ddrc1",
12  				      "ddrc2",
13  				      "ddrphyc",
14  				      "ddrcapb",
15  				      "ddrphycapb";
16  			status = "okay";
17  		};

3.2 DT configuration (board level)[edit]

The next attributes provide the DDR information and DDR settings; the values used by the FSBL to initialize the registers of the DDR subsystem (the DDR controller and the DDR PHY).

These value are generated by DDR tools included in STM32CubeMX.

The board configuration defines each configuration needed (DDR_...) and includes the STM32-level device tree.

3.2.1 info[edit]

  • st,mem-name: name for the DDR configuration, a simple string for information
  • st,mem-speed: DDR expected speed in kHz
  • st,mem-size: DDR mem size in bytes (used in SSBL and FSBL)

3.2.2 Controller register values[edit]

  • st,ctl-reg: controller values depending on the DDR type (DDR3/LPDDR2/LPDDR3):
    • for STM32MP13x lines Warning.png and for STM32MP15x lines More info.png 25 values are requested in this order: (MSTR MRCTRL0 MRCTRL1 DERATEEN DERATEINT PWRCTL PWRTMG HWLPCTL RFSHCTL0 RFSHCTL3 CRCPARCTL0 ZQCTL0 DFITMG0 DFITMG1 DFILPCFG0 DFIUPD0 DFIUPD1 DFIUPD2 DFIPHYMSTR ODTMAP DBG0 DBG1 DBGCMD POISONCFG PCCFG)
  • st,ctl-timing: controller values depending on the DDR frequency and timing parameters:
    • for STM32MP13x lines Warning.png and for STM32MP15x lines More info.png 12 values are requested in this order: (RFSHTMG DRAMTMG0 DRAMTMG1 DRAMTMG2 DRAMTMG3 DRAMTMG4 DRAMTMG5 DRAMTMG6 DRAMTMG7 DRAMTMG8 DRAMTMG14 ODTCFG)
  • st,ctl-map: controller values depending on the address mapping:
    • for STM32MP13x lines Warning.png and for STM32MP15x lines More info.png 9 values are requested in this order: (ADDRMAP1 ADDRMAP2 ADDRMAP3 ADDRMAP4 ADDRMAP5 ADDRMAP6 ADDRMAP9 ADDRMAP10 ADDRMAP11)
  • st,ctl-perf: controller values depending on performance and scheduling:
    • for STM32MP13x lines Warning.png 11 values are requested in this order: (SCHED SCHED1 PERFHPR1 PERFLPR1 PERFWR1 PCFGR_0 PCFGW_0 PCFGQOS0_0 PCFGQOS1_0 PCFGWQOS0_0 PCFGWQOS1_0)
    • for STM32MP15x lines More info.png 17 values are requested in this order: (SCHED SCHED1 PERFHPR1 PERFLPR1 PERFWR1 PCFGR_0 PCFGW_0 PCFGQOS0_0 PCFGQOS1_0 PCFGWQOS0_0 PCFGWQOS1_0 PCFGR_1 PCFGW_1 PCFGQOS0_1 PCFGQOS1_1 PCFGWQOS0_1 PCFGWQOS1_1)

3.2.3 phy register values[edit]

  • st,phy-reg: phy values depending on the DDR type: (DDR3/LPDDR2/LPDDR3):
    • for STM32MP13x lines Warning.png 9 values are requested in this order: (PGCR ACIOCR DXCCR DSGCR DCR ODTCR ZQ0CR1 DX0GCR DX1GCR)
    • for STM32MP15x lines More info.png 11 values are requested in this order: (PGCR ACIOCR DXCCR DSGCR DCR ODTCR ZQ0CR1 DX0GCR DX1GCR DX2GCR DX3GCR)
  • st,phy-timing: phy values depending on the DDR frequency and timing parameters:
    • for STM32MP13x lines Warning.png and for STM32MP15x lines More info.png 10 values are requested in this order: (PTR0 PTR1 PTR2 DTPR0 DTPR1 DTPR2 MR0 MR1 MR2 MR3)
  • st,phy-cal: phy cal depending on the DDR calibration or tuning. This parameter is optional: when it is absent, the built-in PHY calibration is done (see the next chapter for details); when it is present:
    • for STM32MP13x lines Warning.png 6 values are requested in this order: (DX0DLLCR DX0DQTR DX0DQSTR DX1DLLCR DX1DQTR DX1DQSTR)
    • for STM32MP15x lines More info.png 12 values are requested in this order: (DX0DLLCR DX0DQTR DX0DQSTR DX1DLLCR DX1DQTR DX1DQSTR DX2DLLCR DX2DQTR DX2DQSTR DX3DLLCR DX3DQTR DX3DQSTR)
3.2.3.1 st,phy-cal value and DDR tuning[edit]
Warning white.png Warning
It is strongly recommended not to fill the st,phy-cal property and then use the build-in PHY calibration.

By default, the st,phy-cal property is absent in device tree and the built-in PHY calibration is executed by the DDR driver to determine DXnDQTR and DXnDQSTR register values (with n = byte id, 0 to 3).

When st,phy-cal is present in device tree (e.g. when DDR_PHY_CAL_SKIP is defined), the built-in PHY calibration is skipped and the driver use the DXnDQTR and DXnDQSTR values defined in the device tree: they described the fine step delays used for DQ/DQS pin deskew and for eye centering.

See #How to configure the DT using STM32CubeMX and the dedicated application note[5] for further information.

3.3 DT configuration examples[edit]

3.3.1 Simple example[edit]

You can add the DDR configuration node with (STM32MP15x lines More info.png example):

  1   &ddr {
  2   	st,mem-name = "DDR3 2x4Gb 533MHz";
  3   	st,mem-speed = <533000>;
  4   	st,mem-size = <0x40000000>;
  5   
  6   	st,ctl-reg = <
  7   				0x00040401 /*MSTR*/
  8   				0x00000010 /*MRCTRL0*/
  9 	  			0x00000000 /*MRCTRL1*/
 10   				0x00000000 /*DERATEEN*/
 11   				0x00800000 /*DERATEINT*/
 12   				0x00000000 /*PWRCTL*/
 13   				0x00400010 /*PWRTMG*/
 14   				0x00000000 /*HWLPCTL*/
 15   				0x00210000 /*RFSHCTL0*/
 16   				0x00000000 /*RFSHCTL3*/
 17   				0x00000000 /*CRCPARCTL0*/
 18   				0xC2000040 /*ZQCTL0*/
 19   				0x02050105 /*DFITMG0*/
 20   				0x00000202 /*DFITMG1*/
 21   				0x07000000 /*DFILPCFG0*/
 22   				0xC0400003 /*DFIUPD0*/
 23   				0x00000000 /*DFIUPD1*/
 24   				0x00000000 /*DFIUPD2*/
 25   				0x00000000 /*DFIPHYMSTR*/
 26   				0x00000001 /*ODTMAP*/
 27   				0x00000000 /*DBG0*/
 28   				0x00000000 /*DBG1*/
 29   				0x00000000 /*DBGCMD*/
 30   				0x00000000 /*POISONCFG*/
 31   				0x00000010 /*PCCFG*/
 32  	 >;
 33   
 34   	st,ctl-timing = <
 35   				0x0080008A /*RFSHTMG*/
 36   				0x121B2414 /*DRAMTMG0*/
 37   				0x000D041B /*DRAMTMG1*/
 38   				0x0607080E /*DRAMTMG2*/
 39   				0x0050400C /*DRAMTMG3*/
 40   				0x07040407 /*DRAMTMG4*/
 41   				0x06060303 /*DRAMTMG5*/
 42   				0x02020002 /*DRAMTMG6*/
 43   				0x00000202 /*DRAMTMG7*/
 44   				0x00001005 /*DRAMTMG8*/
 45   				0x000D041B /*DRAMTMG14*/
 46   				0x06000600 /*ODTCFG*/
 47   	>;
 48   
 49  	st,ctl-map = <
 50  				0x00080808 /*ADDRMAP1*/
 51  				0x00000000 /*ADDRMAP2*/
 52  				0x00000000 /*ADDRMAP3*/
 53  				0x00001F1F /*ADDRMAP4*/
 54  				0x07070707 /*ADDRMAP5*/
 55  				0x0F070707 /*ADDRMAP6*/
 56  				0x00000000 /*ADDRMAP9*/
 57  				0x00000000 /*ADDRMAP10*/
 58  				0x00000000 /*ADDRMAP11*/
 59  	>;
 60   
 61  	st,ctl-perf = <
 62  				0x00001201 /*SCHED*/
 63  				0x00001201 /*SCHED*/1
 64  				0x01000001 /*PERFHPR1*/
 65  				0x08000200 /*PERFLPR1*/
 66  				0x08000400 /*PERFWR1*/
 67  				0x00010000 /*PCFGR_0*/
 68  				0x00000000 /*PCFGW_0*/
 69  				0x02100B03 /*PCFGQOS0_0*/
 70  				0x00800100 /*PCFGQOS1_0*/
 71  				0x01100B03 /*PCFGWQOS0_0*/
 72  				0x01000200 /*PCFGWQOS1_0*/
 73  				0x00010000 /*PCFGR_1*/
 74  				0x00000000 /*PCFGW_1*/
 75  				0x02100B03 /*PCFGQOS0_1*/
 76  				0x00800000 /*PCFGQOS1_1*/
 77  				0x01100B03 /*PCFGWQOS0_1*/
 78  				0x01000200 /*PCFGWQOS1_1*/
 79  	>;
 80   
 81  	st,phy-reg = <
 82  				0x01442E02 /*PGCR*/
 83  				0x10400812 /*ACIOCR*/
 84  				0x00000C40 /*DXCCR*/
 85  				0xF200001F /*DSGCR*/
 86  				0x0000000B /*DCR*/
 87  				0x00010000 /*ODTCR*/
 88  				0x0000007B /*ZQ0CR1*/
 89  				0x0000CE81 /*DX0GCR*/
 90  				0x0000CE81 /*DX1GCR*/
 91  				0x0000CE81 /*DX2GCR*/
 92  				0x0000CE81 /*DX3GCR*/
 93  	>;
 94   
 95  	st,phy-timing = <
 96  				0x0022A41B /*PTR0*/
 97  				0x047C0740 /*PTR1*/
 98  				0x042D9C80 /*PTR2*/
 99  				0x369477D0 /*DTPR0*/
100  				0x098A00D8 /*DTPR1*/
101  				0x10023600 /*DTPR2*/
102  				0x00000830 /*MR0*/
103  				0x00000000 /*MR1*/
104  				0x00000208 /*MR2*/
105  				0x00000000 /*MR3*/
106  	>;
107   
108 	 status = "okay";
109  };

The optional node st,phy-cal allows to use a calibration result when it is present, for example:

 1  &ddr {
 2 ...
 3   	st,phy-cal = <
 4   		0x40000000 /*DX0DLLCR*/
 5   		0xFFFFFFFF /*DX0DQTR*/
 6   		0x3DB02000 /*DX0DQSTR*/
 7   		0x40000000 /*DX1DLLCR*/
 8   		0xFFFFFFFF /*DX1DQTR*/
 9   		0x3DB02000 /*DX1DQSTR*/
10   		0x40000000 /*DX2DLLCR*/
11   		0xFFFFFFFF /*DX2DQTR*/
12   		0x3DB02000 /*DX2DQSTR*/
13   		0x40000000 /*DX3DLLCR*/
14   		0xFFFFFFFF /*DX3DQTR*/
15   		0x3DB02000 /*DX3DQSTR*/
16   	>;
17 ...
18         };

3.3.2 STM32CubeMX configuration file[edit]

STM32CubeMX generates a .dtsi file with the needed values as defines (named DDR_...), and includes the #Generic DDR dtsi file: as this dtsi file is preprocessed during FSBL compilation, it generates a correct device tree.

For example the file fdts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi is:

 1   / SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
 2   /*
 3    * File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs
 4    * DDR type: DDR3 / DDR3L
 5    * DDR width: 16bits
 6    * DDR density: 4Gb
 7    * System frequency: 533000Khz
 8    * Relaxed Timing Mode: false
 9    * Address mapping type: RBC
10    *
11    * Save Date: 2020.02.20, save Time: 18:45:20
12    */
13   
14   #define DDR_MEM_NAME	"DDR3-DDR3L 16bits 533000kHz"
15   #define DDR_MEM_SPEED	533000
16   #define DDR_MEM_SIZE	0x20000000
17  
18   #define DDR_MSTR 0x00041401
19   #define DDR_MRCTRL0 0x00000010
20   #define DDR_MRCTRL1 0x00000000
21   #define DDR_DERATEEN 0x00000000
22   #define DDR_DERATEINT 0x00800000
23   .....
24   #define DDR_DX2DQSTR 0x3DB02000
25   #define DDR_DX3GCR 0x0000CE80
26   #define DDR_DX3DLLCR 0x40000000
27   #define DDR_DX3DQTR 0xFFFFFFFF
28   #define DDR_DX3DQSTR 0x3DB02000
29   
30   #include "stm32mp15-ddr.dtsi"

NB: the calibration values (DXnDLLCR, DXnDQTR, DXnDQSTR, with n in 1...3) are not used when DDR_PHY_CAL_SKIP is not defined, only the built-in calibration is done.

3.3.3 Generic DDR dtsi file[edit]

The dtsi file used with DDR_ defines is

  • stm32mp13-ddr.dtsi[6] for STM32MP13x lines Warning.png
  • stm32mp15-ddr.dtsi[7] for STM32MP15x lines More info.png

For example, stm32mp15-ddr.dtsi is:

  1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2 /*
  3  * Copyright (C) 2018-2021, STMicroelectronics - All Rights Reserved
  4  */
  5 
  6 &ddr {
  7 	st,mem-name = DDR_MEM_NAME;
  8 	st,mem-speed = <DDR_MEM_SPEED>;
  9 	st,mem-size = <DDR_MEM_SIZE>;
 10 
 11 	st,ctl-reg = <
 12 		DDR_MSTR
 13 		DDR_MRCTRL0
 14 		DDR_MRCTRL1
 15 		DDR_DERATEEN
 16 		DDR_DERATEINT
 17 		DDR_PWRCTL
 18 		DDR_PWRTMG
 19 		DDR_HWLPCTL
 20 		DDR_RFSHCTL0
 21 		DDR_RFSHCTL3
 22 		DDR_CRCPARCTL0
 23 		DDR_ZQCTL0
 24 		DDR_DFITMG0
 25 		DDR_DFITMG1
 26 		DDR_DFILPCFG0
 27 		DDR_DFIUPD0
 28 		DDR_DFIUPD1
 29 		DDR_DFIUPD2
 30 		DDR_DFIPHYMSTR
 31 		DDR_ODTMAP
 32 		DDR_DBG0
 33 		DDR_DBG1
 34 		DDR_DBGCMD
 35 		DDR_POISONCFG
 36 		DDR_PCCFG
 37 	>;
 38 
 39 	st,ctl-timing = <
 40 		DDR_RFSHTMG
 41 		DDR_DRAMTMG0
 42 		DDR_DRAMTMG1
 43 		DDR_DRAMTMG2
 44 		DDR_DRAMTMG3
 45 		DDR_DRAMTMG4
 46 		DDR_DRAMTMG5
 47 		DDR_DRAMTMG6
 48 		DDR_DRAMTMG7
 49 		DDR_DRAMTMG8
 50 		DDR_DRAMTMG14
 51 		DDR_ODTCFG
 52 	>;
 53 
 54 	st,ctl-map = <
 55 		DDR_ADDRMAP1
 56 		DDR_ADDRMAP2
 57 		DDR_ADDRMAP3
 58 		DDR_ADDRMAP4
 59 		DDR_ADDRMAP5
 60 		DDR_ADDRMAP6
 61 		DDR_ADDRMAP9
 62 		DDR_ADDRMAP10
 63 		DDR_ADDRMAP11
 64 	>;
 65 
 66 	st,ctl-perf = <
 67 		DDR_SCHED
 68 		DDR_SCHED1
 69 		DDR_PERFHPR1
 70 		DDR_PERFLPR1
 71 		DDR_PERFWR1
 72 		DDR_PCFGR_0
 73 		DDR_PCFGW_0
 74 		DDR_PCFGQOS0_0
 75 		DDR_PCFGQOS1_0
 76 		DDR_PCFGWQOS0_0
 77 		DDR_PCFGWQOS1_0
 78 		DDR_PCFGR_1
 79 		DDR_PCFGW_1
 80 		DDR_PCFGQOS0_1
 81 		DDR_PCFGQOS1_1
 82 		DDR_PCFGWQOS0_1
 83 		DDR_PCFGWQOS1_1
 84 	>;
 85 
 86 	st,phy-reg = <
 87 		DDR_PGCR
 88 		DDR_ACIOCR
 89 		DDR_DXCCR
 90 		DDR_DSGCR
 91 		DDR_DCR
 92 		DDR_ODTCR
 93 		DDR_ZQ0CR1
 94 		DDR_DX0GCR
 95 		DDR_DX1GCR
 96 		DDR_DX2GCR
 97 		DDR_DX3GCR
 98 	>;
 99 
100 	st,phy-timing = <
101 		DDR_PTR0
102 		DDR_PTR1
103 		DDR_PTR2
104 		DDR_DTPR0
105 		DDR_DTPR1
106 		DDR_DTPR2
107 		DDR_MR0
108 		DDR_MR1
109 		DDR_MR2
110 		DDR_MR3
111 	>;
112 
113 #ifdef DDR_PHY_CAL_SKIP
114 	st,phy-cal = <
115 		DDR_DX0DLLCR
116 		DDR_DX0DQTR
117 		DDR_DX0DQSTR
118 		DDR_DX1DLLCR
119 		DDR_DX1DQTR
120 		DDR_DX1DQSTR
121 		DDR_DX2DLLCR
122 		DDR_DX2DQTR
123 		DDR_DX2DQSTR
124 		DDR_DX3DLLCR
125 		DDR_DX3DQTR
126 		DDR_DX3DQSTR
127 	>;
128 #endif
129 };

4 How to configure the DT using STM32CubeMX[edit]

The STM32CubeMX tool can be used to configure the STM32MPU device and get the corresponding platform configuration device tree files.

The STM32CubeMX supports all the defines described in the above DT bindings documentation paragraph with a generated included file "stm32mp15-mx.dtsi"; it is included in the mx dts file before the #Generic DDR dtsi file . Refer to the STM32CubeMX user manual and the dedicated application note[5] for further information.

See also How_to_create_your_board_device_tree#DDR configuration with STM32CubeMX DDR Tuning Tool.

If you want to use the STM32CubeMX DDR Tuning Tool calibration result, add in the generated files "stm32mp15-mx.dtsi" the line:

1   #define DDR_PHY_CAL_SKIP

5 References[edit]

Please refer to the following links for additional information: