Revision history of "DDRCTRL and DDRPHYC device tree configuration"

Diff selection: Mark the radio boxes of the revisions to compare and hit enter or the button at the bottom.
Legend: (cur) = difference with latest revision, (prev) = difference with preceding revision, m = minor edit.

(newest | oldest) View (newer 50 | ) (20 | 50 | 100 | 250 | 500)
  • (cur | prev) 12:44, 23 June 2023 m . . (16,267 bytes) (0) . . (Text replacement - "STM32MP1 Series" to "STM32MP1 series")

    [Reviewed: 12:47, 23 June 2023 | Registered User | [Expert: Approved, Technical writer: Approved, Maintainer: Approved]]

  • (cur | prev) 09:03, 23 June 2023 . . (16,267 bytes) (+285) . . (Merge articles)

    [Reviewed: 09:04, 23 June 2023 | Registered User | [Expert: Approved, Technical writer: Approved, Maintainer: Approved]]

  • (cur | prev) 14:24, 26 October 2022 m . . (15,982 bytes) (+4)

    [Reviewed: 14:25, 26 October 2022 | Registered User | [Expert: Approved, Technical writer: Approved, Maintainer: Approved]]

  • (cur | prev) 13:57, 26 November 2021 m . . (15,978 bytes) (+50) . . (→ DT configuration (STM32 level))

    [Reviewed: 14:01, 26 November 2021 | Registered User | [Expert: Approved, Technical writer: Approved, Maintainer: Approved]]

  • (cur | prev) 14:16, 17 November 2021 m . . (16,644 bytes) (0) . . (KHz => kHz)

    [Reviewed: 14:17, 17 November 2021 | Registered User | [Expert: Aproved, Technical writer: Approved, Maintainer: Approved]]

  • (cur | prev) 17:43, 22 March 2021 m . . (16,671 bytes) (+1) . . (→ st,phy-cal value and DDR tuning)

    [Reviewed: 10:20, 23 March 2021 | Registered User | [Expert: Aproved, Technical writer: Approved, Maintainer: Approved]]

(newest | oldest) View (newer 50 | ) (20 | 50 | 100 | 250 | 500)