Revision history of "DDRCTRL and DDRPHYC device tree configuration"

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  • (cur | prev) 14:24, 26 October 2022 m . . (15,982 bytes) (+4)

    [Reviewed: 14:25, 26 October 2022 | | [Expert: Approved, Technical writer: Approved, Maintainer: Approved]]
  • (cur | prev) 13:57, 26 November 2021 m . . (15,978 bytes) (+50) . . (→ DT configuration (STM32 level))

    [Reviewed: 14:01, 26 November 2021 | | [Expert: Approved, Technical writer: Approved, Maintainer: Approved]]
  • (cur | prev) 14:16, 17 November 2021 m . . (16,644 bytes) (0) . . (KHz => kHz)

    [Reviewed: 14:17, 17 November 2021 | | [Expert: Aproved, Technical writer: Approved, Maintainer: Approved]]
  • (cur | prev) 17:43, 22 March 2021 m . . (16,671 bytes) (+1) . . (→ st,phy-cal value and DDR tuning)

    [Reviewed: 10:20, 23 March 2021 | | [Expert: Aproved, Technical writer: Approved, Maintainer: Approved]]
  • (cur | prev) 16:28, 16 February 2021 m . . (15,341 bytes) (+30) . . (U-Boot | doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt)

    [Reviewed: 16:29, 16 February 2021 | | [Expert: Aproved, Technical writer: Approved, Maintainer: Approved]]
  • (cur | prev) 16:53, 11 January 2021 m . . (15,311 bytes) (0) . . (1 revision imported)

    [Reviewed: 16:54, 11 January 2021 | ]
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