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This article explains how Coresight IP is composed, how to configure it, and how to use it.

1 Framework purpose[edit]

ARM Coresight products include a wide range of trace macrocells for ARM processors, system and software instrumentation and a comprehensive set of IP blocks to enable the debug & trace of the most complex, multi-core SoCs. ARM has defined an open CoreSight architecture to allow SoC designers to add debug & trace capabilities for other IP cores in to the CoreSight infrastructure.

Coresight can be used in many different use cases, as mentioned in How to use Coresight section

2 System overview[edit]

Alternate text
Coresight Overview

2.1 Component description[edit]

The debug features are based on Arm® CoreSight™ components:
• SWJ-DP: JTAG/Serial-wire debug port
• AXI-AP: AXI access port
• AHB-AP: AHB access port
• APB-AP: APB access port
• ITM: Instrumentation Trace Macrocell
• DWT: Data Watchpoint and Trace
• ETM: Embedded Trace Macrocell
• ETF: Embedded Trace FIFO
• TPIU: Trace Port Interface Unit
• SWO: Serial Wire Output
• CTI: Cross Trigger Interface
• CTM: Cross Trigger Matrix
• Timestamp Generator
• STM: System Trace Macrocell
More information about these components can be found in the Arm® documents referenced [1]

3 Configuration[edit]

3.1 Kernel configuration[edit]

The Coresight feature is activated by default in ST deliveries. Nevertheless, if a specific configuration is required, you can use Linux Menuconfig tool: Menuconfig or how to configure kernel and select:

For Coresight features:


                                                                                                                                          
 [*] Device Drivers                                                                                                                                  
    [*] HW tracing support
        [*] STM (System Trace Module devices)
          [*]  Kernel console over STM devices                                                                         
          [*]  Copy the output from kernel Ftrace to STM engine  
 [*] Kernel hacking
    [*] CoreSight Tracing Support                                                                                  
        [*] CoreSight Link and Sink drivers                                                                          
          [*]  Coresight generic TMC driver                                                                          
          [*]  Coresight generic TPIU driver                                                                        
          [*]  Coresight ETBv1.0 driver                                                                             
        [*]   CoreSight Embedded Trace Macrocell 3.x driver                                                          
        [*]   CoreSight System Trace Macrocell driver                                                                


3.2 Device tree configuration[edit]

DT bindings documentation deals with all required or optional device tree properties.

Detailed DT configuration for STM32 internal peripherals: Coresight device tree configuration.

4 How to use Coresight[edit]

4.1 How to use the Coresight user space interface[edit]

Please see examples based on the following use cases:

5 How to trace and debug the framework[edit]

5.1 How to monitor[edit]

5.1.1 How to monitor with sysfs[edit]

sysfs entry can be used to browse Coresight components.

 Board $> /sys/bus/coresight# ls
devices  drivers  drivers_autoprobe  drivers_probe  uevent

 Board $> /sys/bus/coresight# ls devices/
50091000.funnel  50092000.etf  50093000.tpiu  500a0000.stm  500dc000.etm  500dd000.etm  replicator

5.2 How to trace[edit]

Coresight Framework print out info and error messages. You can display them with dmesg command:

Board $> dmesg | grep coresight
[    2.510368] coresight-etm3x 500dc000.etm: ETM 3.5 initialized
[    2.515415] coresight-etm3x 500dd000.etm: ETM 3.5 initialized
[    2.521087] coresight-stm 500a0000.stm: stm_register_device failed, probing deffered
[    3.065495] coresight-stm 500a0000.stm: STM500 initialized

5.3 How to debug[edit]

6 Source code location[edit]

The source files are located inside the Linux kernel.

7 References[edit]

  1. [1. IHI 0031C (ID080813) - Arm® Debug Interface Architecture Specification ADIv5.0 to ADIv5.2, Issue C, 8th Aug 2013.
    2. DDI 0480F (ID100313) - Arm® CoreSight™ SoC-400 r3p1 Technical Reference Manual, Issue F, 26th Sept 2013.
    3. DDI 0461B (ID010111) - Arm® CoreSight™ Trace Memory Controller r0p1 Technical Reference Manual, Issue B, 10 Dec 2010
    4. DDI 0314H - Arm® CoreSight™ Components Technical Reference Manual, Issue H, 10 July, 2009
    5. DDI 0403D (ID100710) - Arm® v7-M Architecture Reference Manual, Issue Derrata2010_Q3, November 2010
    6. DDI 0468A (ID101712) - Arm® CoreSight™ ETM™-A7 r0p0, Issue A, 12 Sept 2011
    7. DDI 0440C (ID070610) - Arm® CoreSight™ ETM™-M4 r0p1 Technical Reference Manual, Issue C, 29 June 2012
    8. DDI 0528B (ID062514) - Arm® CoreSight™ STM-500 System Trace Macrocell r0p1 Technical Reference Manual, Issue B, 11 March 2014
    9. DDI 0464F (ID051113) - Arm® Cortex®-A7 MPCore™ r0p5 Technical Reference Manual, Issue F, 11 April 2013],Arm® documents referenced



<noinclude>

{{ArticleBasedOnModel|[[Framework overview article model]]}}
{{ArticleMainWriter|ChristopheR}}
{{ArticleApprovedVersion | Jean-ChristopheT | Nobody | No previous approved version | Automatic approval (article under construction) | 28Jan’19}}
[[This article explains how Coresight IP is composed, how to configure it, and how to use it. 

== Framework purpose ==

ARM '''Coresight''' products include a wide range of trace macrocells for ARM processors, system and software instrumentation and a comprehensive set of IP blocks to enable the debug & trace of the most complex, multi-core SoCs.
ARM has defined an open CoreSight architecture to allow SoC designers to add debug & trace capabilities for other IP cores in to the CoreSight infrastructure.

Coresight can be used in many different use cases, as mentioned in [[#How to use Coresight|How to use Coresight]] section

==System overview==
[[File:Coresight_overview.png|thumb|center|766px|alt=Alternate text|Coresight Overview]]

===Component description===

The debug features are based on Arm® CoreSight™ components:<br />

• SWJ-DP: JTAG/Serial-wire debug port<br />

• AXI-AP: AXI access port<br />

• AHB-AP: AHB access port<br />

• APB-AP: APB access port<br />

• ITM: Instrumentation Trace Macrocell<br />

• DWT: Data Watchpoint and Trace<br />

• ETM: Embedded Trace Macrocell<br />

• ETF: Embedded Trace FIFO<br />

• TPIU: Trace Port Interface Unit<br />

• SWO: Serial Wire Output<br />

• CTI: Cross Trigger Interface<br />

• CTM: Cross Trigger Matrix<br />

• Timestamp Generator<br />

• STM: System Trace Macrocell<br />

More information about these components can be found in the Arm® documents referenced <ref>[1. IHI 0031C (ID080813) - Arm® Debug Interface Architecture Specification ADIv5.0 to
ADIv5.2, Issue C, 8th Aug 2013.<br />

2. DDI 0480F (ID100313) - Arm® CoreSight™ SoC-400 r3p1 Technical Reference
Manual, Issue F, 26th Sept 2013.<br />

3. DDI 0461B (ID010111) - Arm® CoreSight™ Trace Memory Controller r0p1 Technical
Reference Manual, Issue B, 10 Dec 2010<br />

4. DDI 0314H - Arm® CoreSight™ Components Technical Reference Manual, Issue H, 10
July, 2009<br />

5. DDI 0403D (ID100710) - Arm® v7-M Architecture Reference Manual, Issue
Derrata2010_Q3, November 2010<br />

6. DDI 0468A (ID101712) - Arm® CoreSight™ ETM™-A7 r0p0, Issue A, 12 Sept 2011<br />

7. DDI 0440C (ID070610) - Arm® CoreSight™ ETM™-M4 r0p1 Technical Reference
Manual, Issue C, 29 June 2012<br />

8. DDI 0528B (ID062514) - Arm® CoreSight™ STM-500 System Trace Macrocell r0p1
Technical Reference Manual, Issue B, 11 March 2014<br />

9. DDI 0464F (ID051113) - Arm® Cortex®-A7 MPCore™ r0p5 Technical Reference
Manual, Issue F, 11 April 2013],Arm® documents referenced<br /></ref>


==Configuration ==
===Kernel configuration===
The Coresight feature is activated by default in ST deliveries. Nevertheless, if a specific configuration is required, you can use Linux Menuconfig tool: [[Menuconfig or how to configure kernel | Menuconfig or how to configure kernel ]] and select:

For Coresight features:<pre>


 [*] Device Drivers                                                                                                                                  
    [*] HW tracing support
        [*] STM (System Trace Module devices)
          [*]  Kernel console over STM devices                                                                         
          [*]  Copy the output from kernel Ftrace to STM engine  
 [*] Kernel hacking
    [*] CoreSight Tracing Support                                                                                  
        [*] CoreSight Link and Sink drivers                                                                          
          [*]  Coresight generic TMC driver                                                                          
          [*]  Coresight generic TPIU driver                                                                        
          [*]  Coresight ETBv1.0 driver                                                                             
        [*]   CoreSight Embedded Trace Macrocell 3.x driver                                                          
        [*]   CoreSight System Trace Macrocell driver                                                                
</pre>


===Device tree configuration===
DT bindings documentation deals with all required or optional [[Device tree|device tree]] properties.

Detailed DT configuration for STM32 internal peripherals: [[Coresight device tree configuration|Coresight device tree configuration]].

==How to use Coresight ==
=== How to use the Coresight user space interface ===
Please see examples based on the following use cases:

==How to trace and debug the framework==
=== How to monitor ===

==== How to monitor with sysfs ====

'''sysfs''' entry can be used to browse Coresight components.

  {{Board$}} /sys/bus/coresight# ls
 devices  drivers  drivers_autoprobe  drivers_probe  uevent

  {{Board$}} /sys/bus/coresight# ls devices/
 50091000.funnel  50092000.etf  50093000.tpiu  500a0000.stm  500dc000.etm  500dd000.etm  replicator

=== How to trace ===
Coresight Framework print out info and error messages. You can display them with dmesg command:
 {{Board$}} '''dmesg | grep coresight'''
 [    2.510368] coresight-etm3x 500dc000.etm: ETM 3.5 initialized
 [    2.515415] coresight-etm3x 500dd000.etm: ETM 3.5 initialized
 [    2.521087] coresight-stm 500a0000.stm: stm_register_device failed, probing deffered
 [    3.065495] coresight-stm 500a0000.stm: STM500 initialized

=== How to debug ===

==Source code location==
The source files are located inside the Linux kernel.

==References==<references />

<noinclude>

[[Category:Embedded trace and debug]]</noinclude>

{{UnderConstruction}}{{ArticleBasedOnModel|Framework overview article model}}
{{ArticleMainWriter|ChristopheR}}</noinclude>
(One intermediate revision by one other user not shown)
Line 1: Line 1:
  +
This article explains how Coresight IP is composed, how to configure it, and how to use it.
  +
  +
== Framework purpose ==
  +
  +
ARM '''Coresight''' products include a wide range of trace macrocells for ARM processors, system and software instrumentation and a comprehensive set of IP blocks to enable the debug & trace of the most complex, multi-core SoCs.
  +
ARM has defined an open CoreSight architecture to allow SoC designers to add debug & trace capabilities for other IP cores in to the CoreSight infrastructure.
  +
  +
Coresight can be used in many different use cases, as mentioned in [[#How to use Coresight|How to use Coresight]] section
  +
  +
==System overview==
  +
[[File:Coresight_overview.png|thumb|center|766px|alt=Alternate text|Coresight Overview]]
  +
  +
===Component description===
  +
  +
The debug features are based on Arm® CoreSight™ components:<br />
  +
• SWJ-DP: JTAG/Serial-wire debug port<br />
  +
• AXI-AP: AXI access port<br />
  +
• AHB-AP: AHB access port<br />
  +
• APB-AP: APB access port<br />
  +
• ITM: Instrumentation Trace Macrocell<br />
  +
• DWT: Data Watchpoint and Trace<br />
  +
• ETM: Embedded Trace Macrocell<br />
  +
• ETF: Embedded Trace FIFO<br />
  +
• TPIU: Trace Port Interface Unit<br />
  +
• SWO: Serial Wire Output<br />
  +
• CTI: Cross Trigger Interface<br />
  +
• CTM: Cross Trigger Matrix<br />
  +
• Timestamp Generator<br />
  +
• STM: System Trace Macrocell<br />
  +
More information about these components can be found in the Arm® documents referenced <ref>[1. IHI 0031C (ID080813) - Arm® Debug Interface Architecture Specification ADIv5.0 to
  +
ADIv5.2, Issue C, 8th Aug 2013.<br />
  +
2. DDI 0480F (ID100313) - Arm® CoreSight™ SoC-400 r3p1 Technical Reference
  +
Manual, Issue F, 26th Sept 2013.<br />
  +
3. DDI 0461B (ID010111) - Arm® CoreSight™ Trace Memory Controller r0p1 Technical
  +
Reference Manual, Issue B, 10 Dec 2010<br />
  +
4. DDI 0314H - Arm® CoreSight™ Components Technical Reference Manual, Issue H, 10
  +
July, 2009<br />
  +
5. DDI 0403D (ID100710) - Arm® v7-M Architecture Reference Manual, Issue
  +
Derrata2010_Q3, November 2010<br />
  +
6. DDI 0468A (ID101712) - Arm® CoreSight™ ETM™-A7 r0p0, Issue A, 12 Sept 2011<br />
  +
7. DDI 0440C (ID070610) - Arm® CoreSight™ ETM™-M4 r0p1 Technical Reference
  +
Manual, Issue C, 29 June 2012<br />
  +
8. DDI 0528B (ID062514) - Arm® CoreSight™ STM-500 System Trace Macrocell r0p1
  +
Technical Reference Manual, Issue B, 11 March 2014<br />
  +
9. DDI 0464F (ID051113) - Arm® Cortex®-A7 MPCore™ r0p5 Technical Reference
  +
Manual, Issue F, 11 April 2013],Arm® documents referenced<br /></ref>
  +
  +
==Configuration ==
  +
===Kernel configuration===
  +
The Coresight feature is activated by default in ST deliveries. Nevertheless, if a specific configuration is required, you can use Linux Menuconfig tool: [[Menuconfig or how to configure kernel | Menuconfig or how to configure kernel ]] and select:
  +
  +
For Coresight features:
  +
<pre>
  +
                                                                                                                                         
  +
[*] Device Drivers                                                                                                                                 
  +
    [*] HW tracing support
  +
        [*] STM (System Trace Module devices)
  +
          [*]  Kernel console over STM devices                                                                       
  +
          [*]  Copy the output from kernel Ftrace to STM engine 
  +
[*] Kernel hacking
  +
    [*] CoreSight Tracing Support                                                                                 
  +
        [*] CoreSight Link and Sink drivers                                                                         
  +
          [*]  Coresight generic TMC driver                                                                         
  +
          [*]  Coresight generic TPIU driver                                                                       
  +
          [*]  Coresight ETBv1.0 driver                                                                           
  +
        [*]  CoreSight Embedded Trace Macrocell 3.x driver                                                         
  +
        [*]  CoreSight System Trace Macrocell driver                                                               
  +
  +
</pre>
  +
  +
===Device tree configuration===
  +
DT bindings documentation deals with all required or optional [[Device tree|device tree]] properties.
  +
  +
Detailed DT configuration for STM32 internal peripherals: [[Coresight device tree configuration|Coresight device tree configuration]].
  +
  +
==How to use Coresight ==
  +
=== How to use the Coresight user space interface ===
  +
Please see examples based on the following use cases:
  +
  +
==How to trace and debug the framework==
  +
=== How to monitor ===
  +
  +
==== How to monitor with sysfs ====
  +
  +
'''sysfs''' entry can be used to browse Coresight components.
  +
  +
  {{Board$}} /sys/bus/coresight# ls
  +
devices  drivers  drivers_autoprobe  drivers_probe  uevent
  +
  +
  {{Board$}} /sys/bus/coresight# ls devices/
  +
50091000.funnel  50092000.etf  50093000.tpiu  500a0000.stm  500dc000.etm  500dd000.etm  replicator
  +
  +
=== How to trace ===
  +
Coresight Framework print out info and error messages. You can display them with dmesg command:
  +
{{Board$}} '''dmesg | grep coresight'''
  +
[    2.510368] coresight-etm3x 500dc000.etm: ETM 3.5 initialized
  +
[    2.515415] coresight-etm3x 500dd000.etm: ETM 3.5 initialized
  +
[    2.521087] coresight-stm 500a0000.stm: stm_register_device failed, probing deffered
  +
[    3.065495] coresight-stm 500a0000.stm: STM500 initialized
  +
  +
=== How to debug ===
  +
  +
==Source code location==
  +
The source files are located inside the Linux kernel.
  +
  +
==References==
  +
<references />
  +
 
<noinclude>
 
<noinclude>
{{ArticleBasedOnModel|[[Framework overview article model]]}}
+
[[Category:Embedded trace and debug]]
  +
{{ArticleBasedOnModel|Framework overview article model}}
 
{{ArticleMainWriter|ChristopheR}}
 
{{ArticleMainWriter|ChristopheR}}
{{ArticleApprovedVersion | Jean-ChristopheT | Nobody | No previous approved version | Automatic approval (article under construction) | 28Jan’19}}
 
[[Category:Embedded trace and debug]]
 
 
</noinclude>
 
</noinclude>
{{UnderConstruction}}
 

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