BSEC internal peripheral

Applicable for STM32MP13x lines, STM32MP15x lines

1 Article purpose[edit]

The purpose of this article is to

  • briefly introduce the BSEC peripheral and its main features
  • indicate the level of security supported by this hardware block
  • explain how each instance can be allocated to the runtime contexts and linked to the corresponding software components
  • explain, when necessary, how to configure the BSEC peripheral.

2 Peripheral overview[edit]

The BSEC peripheral is used to control an OTP (one time programmable) fuse box, used for on-chip non-volatile storage for device configuration and security parameters.

2.1 Features[edit]

Refer to STM32MP13 reference manuals or STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to see which features are implemented.

2.2 Security support[edit]

The BSEC is a secure peripheral.

3 Peripheral usage and associated software[edit]

3.1 Boot time[edit]

The BSEC is configured at boot time to set up platform security.

3.2 Runtime[edit]

3.2.1 Overview[edit]

The BSEC is a system peripheral and is controlled by the Arm® Cortex®-A7 secure:

Info white.png Information
  • BSEC lower OTP access can be made available to the Arm® Cortex®-A7 non-secure.
  • Upper OTP access can be managed as exceptions:
  • on STM32MP13x lines Warning.png, using OP-TEE PTA
  • on STM32MP15x lines More info.png, using TF-A "secure monitor calls" or OP-TEE PTA

Please refer to BSEC device tree configuration for more details.

3.2.2 Software frameworks[edit]

3.2.2.1 On STM32MP13x lines Warning.png[edit]
Domain Peripheral Software components Comment
OP-TEE Linux
Security BSEC OP-TEE OTP PTA Linux NVMEM framework
3.2.2.2 On STM32MP15x lines More info.png[edit]
Domain Peripheral Software components Comment
OP-TEE Linux STM32Cube
Security BSEC OP-TEE OTP PTA Linux NVMEM framework

3.2.3 Peripheral configuration[edit]

The configuration is based on Device tree, please refer to BSEC device tree configuration article.
It can be applied by the firmware running in a secure context, done in TF-A or in OP-TEE.
It can also be configured by Linux® kernel, please refer to NVMEM overview article.

3.2.4 Peripheral assignment[edit]

3.2.4.1 On STM32MP13x lines Warning.png[edit]

Click on the right to expand the legend...

STM32MP13IPsOverview.png

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

  • means that the peripheral can be assigned () to the given runtime context.
  • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
  • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP13 reference manuals.

Domain Peripheral Runtime allocation Comment
Instance Cortex-A7
secure
(OP-TEE)
Cortex-A7
non-secure
(Linux)
Security BSEC BSEC
3.2.4.2 On STM32MP15x lines More info.png[edit]

Click on the right to expand the legend...

STM32MP15 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

  • means that the peripheral can be assigned () to the given runtime context.
  • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
  • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain Peripheral Runtime allocation Comment
Instance Cortex-A7
secure
(OP-TEE)
Cortex-A7
non-secure
(Linux)
Cortex-M4

(STM32Cube)
Security BSEC BSEC

4 How to go further[edit]

5 References[edit]