Difference between revisions of "BKPSRAM internal memory"

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1 Peripheral overview[edit]

The BKPSRAM internal memory is 4 Kbytes wide and is located in the VSW power domain, allowing it to be supplied during Standby low power mode, or to be switched off.

1.1 Features[edit]

Refer to STM32MP15 reference manuals for the complete feature list, and to the software components introduced below, to see which features are currently implemented.

1.2 Security support[edit]

The BKPSRAM is a secure peripheral (under ETZPC control).

2 Peripheral usage and associated software[edit]

2.1 Boot time[edit]

The BKPSRAM internal memory is not used during a cold boot or a wake up from Standby with DDR OFF.

The BKPSRAM internal memory is used by the runtime secure monitor (from the FSBL or the OP-TEE secure OS) during wake-up from Standby low power mode with the DDR in Self-Refresh mode. In that case, the BKPSRAM internal memory contains the secure context that has to be restored before jumping back to Linux execution, in DDR.

2.2 Runtime[edit]

2.2.1 Overview[edit]

The BKPSRAM peripheral can be allocated to:

  • the Arm® Cortex®-A7 secure to be used under PSCI [1] secure services (from the FSBL or OP-TEE secure monitor) to save the secure context before entering STANDBY low power mode with DDR in Self-Refresh mode. This is the default assignement.

or

  • the Cortex-A7 non-secure to be used under Linux® as reserved memory, for instance.

2.2.2 Software frameworks[edit]

Domain Peripheral Software frameworks Comment
Cortex-A7
secure
(OP-TEE)
Cortex-A7
non-secure
(Linux)
Cortex-M4

(STM32Cube)
Core/RAM BKPSRAM TF-A overview Linux reserved memory

2.2.3 Peripheral configuration[edit]

The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration by itself can be done via the STM32CubeMX tool for all internal peripherals, and can then be manually be completed (particularly for external peripherals), according to the information given in the corresponding software framework article.

2.2.4 Peripheral assignment[edit]

Internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

  • means that the peripheral can be assigned () to the given runtime context.
  • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain Peripheral Runtime allocation Comment
Instance Cortex-A7
secure
(OP-TEE)
Cortex-A7
non-secure
(Linux)
Cortex-M4

(STM32Cube)
Core/RAM BKPSRAM BKPSRAM Assignment (single choice)

3 How to go further[edit]4 References[edit]



<noinclude>

{{ArticleBasedOnModel| [[Internal peripheral article model]]}}
{{ArticleMainWriter|GeraldB}}
{{ ArticleApprovedVersion| GeraldB | OlivierB, LionelD, NathalieS |No previous approved version| PhilipS - 29'Aug18 - 8335 | 4Sep'18 }} 

[[Category:RAM interfaces]]

{{ReviewsComments|JCT 1840: alignment needed with the last version of the model [[Internal peripheral article model]]<br>

[[Category:ToBeAlignedWithModel]]
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==Peripheral overview==
The '''BKPSRAM''' internal memory is 4 Kbytes wide and is located in the VSW power domain, allowing it to be supplied during Standby [[Power overview|low power mode]], or  to be switched off.

===Features===
Refer to [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete feature list, and to the software components introduced below, to see which features are currently implemented.<br>


===Security support===
The BKPSRAM is a '''secure ''' peripheral (under [[ETZPC_internal_peripheral|ETZPC]] control).

==Peripheral usage and associated software==
===Boot time===
The BKPSRAM internal memory is not used during a [[Boot chains overview|cold boot]] or a wake up from Standby with [[DDRCTRL and DDRPHYC internal peripherals|DDR]] OFF.

The BKPSRAM internal memory is used by the runtime secure monitor (from the [[Boot chains overview|FSBL]] or the [[OP-TEE overview|OP-TEE secure OS]]) during wake-up from Standby [[Power overview|low power mode]] with the [[DDRCTRL and DDRPHYC internal peripherals|DDR]] in Self-Refresh mode. In that case, the BKPSRAM internal memory contains the secure context that has to be restored before jumping back to Linux execution, in [[DDRCTRL and DDRPHYC internal peripherals|DDR]].

===Runtime===
====Overview====
The BKPSRAM peripheral can be allocated to:
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 secure to be used under PSCI <ref>http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf</ref> secure services (from the [[Boot chains overview|FSBL]] or [[OP-TEE overview|OP-TEE]] secure monitor) to save the secure context before entering STANDBY [[Power overview|low power mode]] with DDR in Self-Refresh mode. This is the default assignement.
or
* the Cortex-A7 non-secure to be used under Linux<sup>&reg;</sup> as [[Reserved memory|reserved memory]], for instance.

====Software frameworks====
{{:Internal_peripherals_software_table_template}}
 | Core/RAM
 | [[BKPSRAM internal memory|BKPSRAM]]
 | [[TF-A overview#BL32|TF-A overview]]
 | [[Reserved memory|Linux reserved memory]]
 |
 |
 |-
 |}

====Peripheral configuration====
The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration by itself can be done via the [[STM32CubeMX]] tool for all internal peripherals, and can then be manually be completed (particularly for external peripherals), according to the information given in the corresponding software framework article.

====Peripheral assignment====
{{:Internal_peripherals_assignment_table_template}}<onlyinclude>

 | rowspan="1" | Core/RAM
 | rowspan="1" | [[BKPSRAM internal memory|BKPSRAM]]
 | BKPSRAM
 | <span title="assignable peripheral" style="font-size:21px"></span>

 | <span title="assignable peripheral" style="font-size:21px"></span>

 |
 | Assignment (single choice)
 |-</onlyinclude>

 |}


==How to go further==

==References==<references/>==References==<references/>

<noinclude>

[[Category:RAM interfaces]]
{{PublicationRequestId | 8335 | 2018-08-29 | PhilipS}}
{{ArticleBasedOnModel| Internal peripheral article model}}
{{ReviewsComments|JCT 1840: alignment needed with the last version of the model<br>

[[Category:ToBeAlignedWithModel]]
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{{ArticleBasedOnModel| [[Internal peripheral article model]]}}
 
{{ArticleMainWriter|GeraldB}}
 
{{ ArticleApprovedVersion| GeraldB | OlivierB, LionelD, NathalieS |No previous approved version| PhilipS - 29'Aug18 - 8335 | 4Sep'18 }}
 
 
[[Category:RAM interfaces]]
 
 
{{ReviewsComments|JCT 1840: alignment needed with the last version of the model [[Internal peripheral article model]]<br>
 
[[Category:ToBeAlignedWithModel]]
 
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==Peripheral overview==
 
==Peripheral overview==
 
The '''BKPSRAM''' internal memory is 4 Kbytes wide and is located in the VSW power domain, allowing it to be supplied during Standby [[Power overview|low power mode]], or  to be switched off.
 
The '''BKPSRAM''' internal memory is 4 Kbytes wide and is located in the VSW power domain, allowing it to be supplied during Standby [[Power overview|low power mode]], or  to be switched off.
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==How to go further==
 
   
 
==References==
 
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[[Category:RAM interfaces]]
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{{PublicationRequestId | 8335 | 2018-08-29 | PhilipS}}
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{{ArticleBasedOnModel| Internal peripheral article model}}
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{{ReviewsComments|JCT 1840: alignment needed with the last version of the model<br>
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