Difference between revisions of "Arm CoreSight overview"

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1 Article purpose[edit]

The purpose of this article is to provide information on the Arm® CoreSight hardware subsystem.
It explains what are the principle peripherals of this subsystem.

2 Peripheral overview[edit]

To enable the debug and trace of the most complex, multi-core SoCs, Arm®CoreSight products include

  • a wide range of trace macrocells for Arm® processors,
  • a system and software instrumentation,
  • and a comprehensive set of IP blocks.

Arm® has defined an open CoreSight architecture to allow SoC designers to add "debug and trace" capabilities for other IP cores in to the CoreSight infrastructure.

Alternate text
CoreSight overview

2.1 Components description[edit]

The debug features are based on Arm® CoreSight™ components:
• SWJ-DP: JTAG/Serial-wire debug port
• AXI-AP: AXI access port
• AHB-AP: AHB access port
• APB-AP: APB access port
• ITM: Instrumentation Trace Macrocell
• DWT: Data Watchpoint and Trace
• ETM: Embedded Trace Macrocell
• ETF: Embedded Trace FIFO
• TPIU: Trace Port Interface Unit
• SWO: Serial Wire Output
• CTI: Cross Trigger Interface
• CTM: Cross Trigger Matrix
• TSGEN: Timestamp Generator
• STM: System Trace Macrocell
More information about these components can be found in the Arm® website [1]

2.2 Features[edit]

Refer to the STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to see which features are really implemented.

3 References[edit]


==Article purpose==
The purpose of this article is to provide information on the Arm<sup>&reg;</sup> CoreSight<sup>&trade;</sup> hardware subsystem.<br />

It explains what are the principle peripherals of this subsystem.<br />


==Peripheral overview==
To enable the debug and trace of the most complex, multi-core SoCs,  Arm<sup>&reg;</sup> '''CoreSight<sup>&trade;</sup> ''' products include 
* a wide range of trace macrocells for Arm<sup>&reg;</sup> processors, 
* a system and software instrumentation, 
* and a comprehensive set of IP blocks.

Arm<sup>&reg;</sup> has defined an open CoreSight architecture to allow SoC designers to add "debug and trace" capabilities for other IP cores in to the CoreSight<sup>&trade;</sup> infrastructure.<br />


[[File:Coresight_overview.png|thumb|center|766px|alt=Alternate text|CoreSight overview]]

===Components description===
The debug features are based on Arm® CoreSight™ components:<br />

• SWJ-DP: JTAG/Serial-wire debug port<br />

• AXI-AP: AXI access port<br />

• AHB-AP: AHB access port<br />

• APB-AP: APB access port<br />

• ITM: Instrumentation Trace Macrocell<br />

• DWT: Data Watchpoint and Trace<br />

• ETM: [[ETM internal peripheral|Embedded Trace Macrocell]]<br />

• ETF: Embedded Trace FIFO<br />

• TPIU: Trace Port Interface Unit<br />

• SWO: Serial Wire Output<br />

• CTI: Cross Trigger Interface<br />

• CTM: Cross Trigger Matrix<br />

• TSGEN: [[TSGEN internal peripheral|Timestamp Generator]]<br />

• STM: [[STM internal peripheral|System Trace Macrocell]]<br />

More information about these components can be found in the Arm<sup>&reg;</sup> website <ref>https://developer.arm.com/ip-products/system-ip/coresight-debug-and-trace<br />
</ref>


===Features===
Refer to the [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software components, introduced below, to see which features are really implemented.<br>


==References==<references />
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