Difference between revisions of "How to change the CPU frequency"

[quality revision] [quality revision]
m (PLL1 static configuration)
 

1 Purpose[edit]

This article explains how to change the CPU operating point (also known as OPP). An operating point corresponds to the frequency of the processor and the voltage that needs to be supplied to sustain it.
It also shows how it is possible to define multiple operating points, allowing the system to jump among them at run time: this is the dynamic voltage and frequency scaling (DVFS). Some cautions are given at the end of the article, to help the user in its DVFS deployment.

2 Hardware side[edit]

On STM32MP1 Series products, the Cortex-A7 core is:

  • clocked by PLL1 from the RCC internal peripheral. The PLL1P output frequency can be directly propagated to the core, or it can go through an intermediate MPUDIV divider
  • supplied with VDDcore voltage.

The part number tells which devices can be clocked up to 800 MHz, with associated usage conditions. Otherwise, the frequency must be kept below 650 MHz.

3 Software side[edit]

3.1 For ecosystem release ≥ v1.2.0 Overview[edit]

The ecosystem release ≥ v1.2.0 is backward compatible with the previous deliveries, so it is still possible Two ways are offered to the user in order to set the CPU frequency:

  • By default, in
the TF-A device tree, as described in the paragraph below. If
  • OpenSTLinux distribution, the "soc extension" device tree file defines an OPP table that contains one or several frequency / voltage pair(s)
  • Nevertheless, it is possible to directly define the expected PLL1 static configuration in the FSBL device tree
Info white.png Information
Whatever the implementation is, if your part number supports up to 800 MHz, ensure that the VDDcore minimum voltage is increased from 1.2V to 1.35 V while running above 650 MHz
; this is done in the regulators node of the board device tree.
By default however, the ecosystem release ≥ v1.2.0 does not set any configuration for PLL1 in the FSBL (TF-A). Instead

3.2 OPP table[edit]

At boot time, TF-A automatically selects the fastest operating point that is suitable for the current part number according to the OPP table code below (embedding frequency and voltage couples) defined in the SOC extension device tree (fdts/stm32mp157cstm32mp15xa.dtsi or fdts/stm32mp15xd.

cpu0_opp_table: cpu0-opp-table { compatible = "operating-points-v2"; opp-shared; opp-650000000

dtsi ).
At runtime, the Linux will automatically switch between the available operating points according to the CPU load and thanks to Linux cpufreq framework, configured with "ondemand" governor policy (see Documentation/admin-guide/pm/cpufreq.rst ). This feature is called dynamic voltage and frequency scaling (DVFS).

For instance, in the example below, two operating points ([800 MHz ; 1.35 V]; [400 MHz ; 1.2 V]) are defined for a 800 MHz capable part number (opp-supported-hw = <0x2>), so TF-A will apply the [800 MHz ; 1.35 V] configuration at boot time and Linux will then dynamically jump between the two operating points ([800 MHz ; 1.35 V]; [400 MHz ; 1.2 V]) depending on the CPU load.

&cpu0_opp_table {
		opp-800000000 {
			opp-hz = /bits/ 64 <650000000800000000>;
			opp-microvolt = <12000001350000>;
			opp-supported-hw = <0x10x2>;
		};
		opp-800000000400000000 {
			opp-hz = /bits/ 64 <800000000400000000>;
			opp-microvolt = <13500001200000>;
			opp-supported-hw = <0x2>;
		}	opp-suspend;
		};
};

Notes:

  • The operating point(s) supported by devices supporting able to run above 650 MHz (and up to 800 MHz) is/are identified by the opp-supported-hw property set to 0x2.
  • This same OPP table must also be present in the Linux SOC device tree arch/arm/boot/dts/stm32mp157c.dtsi .It is possible to do a mix, specifying the PLL1 configuration (without an OPP table) in the both the TF-A and Linux device tree, whereas Linux uses the OPP table to increase the CPU frequency, once started.
  • This description is valid for cold boot, but also when coming back from Standby low power mode.
  • During cold boot, TF-A computes and saves the PLL1 settings for all operating points available in the device tree in compliance with the hardware capabilities. These saved paramaters are used later to increase the performance of the system-state transitions.

3.2 For ecosystem release ≤ v1.1.03 PLL1 static configuration[edit]

The Cortex-A7 core frequency is selected at boot time, by the FSBL (TF-A), following the Clock device tree configuration - Bootloader specific syntax. The frequency is set to 650 MHz by default, as shown in STM32MP15 clock tree. This configuration is set in the TF-A device tree, for instance fdts/stm32mp157a-dk1.dts file for STM32MP157C-DK1 board.

&rcc {
	...
	/* VCO = 1300.0 MHz => P = 650 (CPU) */
	pll1: st,pll@0 {
		cfg = < 2 80 0 0 0 PQR(1,0,0) >;
		frac = < 0x800 >;
	};
	...
};

The user can reduce this frequency by changing the above configuration, either manually or via the STM32CubeMX graphical user interface that allows generation of the corresponding device tree file.
Notes:

  • The VDDcore voltage is specified in the regulators node of the board device tree, and it has to be kept consistent with the selected frequency, as explained in the overview above.
  • When the PLL1 static configuration is used, TF-A ignores the OPP table (see previous chapter) that may also be present in the device tree, so the secure monitor won't be able to answer to any upcoming frequency switch from Linux. It is therefore recommended to keep only one OPP in the table given to Linux, corresponding to the frequency setup by TF-A at boot time.

4 Dynamic voltage and frequency scaling (DVFS) caution[edit]

  • As stated above, as soon as at least two operating points are defined in the OPP table, Linux kernel will automatically switch between them at runtime thanks to Linux cpufreq framework, configured with "ondemand" governor policy (see Documentation/admin-guide/pm/cpufreq.rst ). It is important to notice that cpufreq framework is only monitoring the CPU load to select the OPP because this can lead to some limitation during use cases where the CPU is not loaded a lot but high reactivity is needed to respect some real time constraints, like interrupt management. If you face some system issue where the CPU reactivity may be the root cause whereas DVFS is enabled, consider doing a trial with "performance" governor (see Documentation/admin-guide/pm/cpufreq.rst ).
  • Selecting OPP frequencies that can be reached with RCC MPUDIV dividor and without configuring again the PLL1 is recommended in order to get the fastest switch time between the OPP.


==Purpose==
This article explains how to change the CPU '''operating point''' (also known as OPP). An operating point corresponds to the '''frequency''' of the processor and the  '''voltage''' that needs to be supplied to sustain it.

<br>

It also shows how it is possible to define multiple operating points, allowing the system to jump among them at run time: this is the '''dynamic voltage and frequency scaling (DVFS)'''. Some cautions are given at the end of the article, to help the user in its DVFS deployment.
==Hardware side==
On {{MicroprocessorDevice | device=1}} products, the Cortex-A7 core is:
* clocked by PLL1 from the [[RCC internal peripheral]]. The PLL1P output '''frequency''' can be directly propagated to the core, or it can go through an intermediate MPUDIV divider
* supplied with VDDcore '''voltage'''.
The [[STM32MP15_microprocessor#Part_number_codification|part number]] tells which devices can be clocked up to 800 MHz, with associated usage conditions. Otherwise, the frequency must be kept below 650 MHz.

==Software side==
===For {{EcosystemRelease | revision=1.2.0 | range=and after}}===
The {{EcosystemRelease | revision=1.2.0 | range=and after}} is backward compatible with the previous deliveries, so it is still possible to set the CPU '''frequency''' in the TF-A device tree, as described in the paragraph below. IfOverview===
Two ways are offered to the user in order to set the CPU frequency:
* By default, in OpenSTLinux distribution, the [[STM32MP15 device tree|"soc extension" device tree]] file defines an '''OPP table''' that contains one or several frequency / voltage pair(s)
* Nevertheless, it is possible to directly define the expected '''PLL1 static configuration''' in the FSBL device tree

{{Info | Whatever the implementation is, if your [[STM32MP15_microprocessor#Part_number_codification|part number]] supports up to 800 MHz, ensure that the VDDcore minimum '''voltage''' is increased from 1.2V to 1.35 V while running above 650 MHz; this is done in the '''regulators''' node of the board device tree.<br>


By default however, the {{EcosystemRelease | revision=1.2.0 | range=and after}} does not set any configuration for PLL1 in the FSBL (TF-A). Instead}}

===OPP table===
At boot time, TF-A automatically selects the '''fastest''' operating point that is suitable for the current [[STM32MP15_microprocessor#Part_number_codification|part number]] according to the OPP table code below (embedding ('''frequency''' and '''voltage''' couples) defined in the SOC extension device tree ({{CodeSource | TF-A | fdts/stm32mp157cstm32mp15xa.dtsi}}.<syntaxhighlight lang="c">

	cpu0_opp_table: cpu0-opp-table {
		compatible = "operating-points-v2";
		opp-shared;

		opp-650000000 or {{CodeSource | TF-A | fdts/stm32mp15xd.dtsi}}).<br>

At runtime, the Linux will automatically switch between the available operating points according to the CPU load and thanks to Linux cpufreq framework, configured with "ondemand" governor policy (see {{CodeSource | Linux kernel | Documentation/admin-guide/pm/cpufreq.rst}}). This feature is called dynamic voltage and frequency scaling (DVFS).<br>


For instance, in the example below, two operating points ([800 MHz ; 1.35 V]; [400 MHz ; 1.2 V]) are defined for a 800 MHz capable part number (opp-supported-hw = <0x2>), so TF-A will apply the [800 MHz ; 1.35 V] configuration at boot time and Linux will then dynamically jump between the two operating points ([800 MHz ; 1.35 V]; [400 MHz ; 1.2 V]) depending on the CPU load.<syntaxhighlight lang="c">

&cpu0_opp_table {
		opp-800000000 {
			opp-hz = /bits/ 64 <650000000><800000000>;
			opp-microvolt = <1200000><1350000>;
			opp-supported-hw = <0x1><0x2>;
		};
		opp-800000000400000000 {
			opp-hz = /bits/ 64 <800000000><400000000>;
			opp-microvolt = <1350000><1200000>;
			opp-supported-hw = <0x2>;};
	};	opp-suspend;
		};
};</syntaxhighlight>

Notes:
* The operating point(s) supported by devices supporting able to run above 650 MHz (and up to 800 MHz) is/are identified by the '''opp-supported-hw''' property set to 0x2.
* This same OPP table must also be present in the Linux SOC device tree {{CodeSource | Linux kernel | arch/arm/boot/dts/stm32mp157c.dtsi}}.
* It is possible to do a mix, specifying the PLL1 configuration (without an OPP table) in the TF-A device tree, whereas Linux uses the OPP table to increase the CPU frequency, once started.both the TF-A and Linux device tree* This description is valid for cold boot, but also when coming back from [[Power overview|Standby]] low power mode.
* During cold boot, TF-A computes and saves the PLL1 settings for all operating points available in the device tree in compliance with the hardware capabilities. These saved paramaters are used later to increase the performance of the system-state transitions.

===For {{EcosystemRelease | revision=1.1.0 | range=and before}}===PLL1 static configuration===

The Cortex-A7 core frequency is selected at boot time, by the FSBL (TF-A), following the [[Clock device tree configuration - Bootloader specific]] syntax. The frequency is set to 650 MHz by default, as shown in [[STM32MP15 clock tree]]. This configuration is set in the TF-A device tree, for instance {{CodeSource | TF-A | fdts/stm32mp157a-dk1.dts}}  file for STM32MP157C-DK1 board.<br>
<syntaxhighlight lang="c">

&rcc {
	...
	/* VCO = 1300.0 MHz => P = 650 (CPU) */
	pll1: st,pll@0 {
		cfg = < 2 80 0 0 0 PQR(1,0,0) >;
		frac = < 0x800 >;
	};
	...
};</syntaxhighlight>

The user can reduce this frequency by changing the above configuration, either manually or via the  [[STM32CubeMX]] graphical user interface that allows generation of the corresponding device tree file.
<br>

Notes:
* The VDDcore voltage is specified in the '''regulators''' node of the board device tree, and it has to be kept consistent with the selected frequency, as explained in the [[#Overview|overview]] above.
* When the PLL1 static configuration is used, TF-A ignores the OPP table (see previous chapter) that may also be present in the device tree, so the secure monitor won't be able to answer to any upcoming frequency switch from Linux. It is therefore recommended to keep only one OPP in the table given to Linux, corresponding to the frequency setup by TF-A at boot time.

==Dynamic voltage and frequency scaling (DVFS) caution==
* As stated above, as soon as at least two operating points are defined in the OPP table, Linux kernel will automatically switch between them at runtime thanks to Linux cpufreq framework, configured with "ondemand" governor policy (see {{CodeSource | Linux kernel | Documentation/admin-guide/pm/cpufreq.rst}}). It is important to notice that cpufreq framework is only monitoring the CPU load to select the OPP because this can lead to some limitation during use cases where the CPU is not loaded a lot but high reactivity is needed to respect some real time constraints, like interrupt management. If you face some system issue where the CPU reactivity may be the root cause whereas DVFS is enabled, consider doing a trial with "performance" governor (see {{CodeSource | Linux kernel | Documentation/admin-guide/pm/cpufreq.rst}}).
* Selecting OPP frequencies that can be reached with [[RCC internal peripheral|RCC]] MPUDIV dividor and without configuring again the PLL1 is recommended in order to get the fastest switch time between the OPP. <noinclude>

[[Category:How to customize software]]
{{PublicationRequestId | 14900 | 2020-02-11 | AnneJ}}</noinclude>
(19 intermediate revisions by 3 users not shown)
Line 1: Line 1:
 
==Purpose==
 
==Purpose==
This article explains how to change the CPU '''operating point''' (also known as OPP). An operating point corresponds to the '''frequency''' of the processor and the  '''voltage''' that needs to be supplied to sustain it.
+
This article explains how to change the CPU '''operating point''' (also known as OPP). An operating point corresponds to the '''frequency''' of the processor and the  '''voltage''' that needs to be supplied to sustain it.<br>
  +
It also shows how it is possible to define multiple operating points, allowing the system to jump among them at run time: this is the '''dynamic voltage and frequency scaling (DVFS)'''. Some cautions are given at the end of the article, to help the user in its DVFS deployment.
   
 
==Hardware side==
 
==Hardware side==
Line 9: Line 10:
   
 
==Software side==
 
==Software side==
===For {{EcosystemRelease | revision=1.2.0 | range=and after}}===
+
===Overview===
The {{EcosystemRelease | revision=1.2.0 | range=and after}} is backward compatible with the previous deliveries, so it is still possible to set the CPU '''frequency''' in the TF-A device tree, as described in the paragraph below. If your [[STM32MP15_microprocessor#Part_number_codification|part number]] supports up to 800 MHz, ensure that the VDDcore minimum '''voltage''' is increased from 1.2V to 1.35 V while running above 650 MHz; this is done in the '''regulators''' node of the board device tree.<br>
+
Two ways are offered to the user in order to set the CPU frequency:
  +
* By default, in OpenSTLinux distribution, the [[STM32MP15 device tree|"soc extension" device tree]] file defines an '''OPP table''' that contains one or several frequency / voltage pair(s)
  +
* Nevertheless, it is possible to directly define the expected '''PLL1 static configuration''' in the FSBL device tree
   
By default however, the {{EcosystemRelease | revision=1.2.0 | range=and after}} does not set any configuration for PLL1 in the FSBL (TF-A). Instead, TF-A automatically selects the operating point that is suitable for the current [[STM32MP15_microprocessor#Part_number_codification|part number]] according to the OPP table code below (embedding '''frequency''' and '''voltage''' couples) defined in the SOC device tree {{CodeSource | TF-A | fdts/stm32mp157c.dtsi}}.
+
{{Info | Whatever the implementation is, if your [[STM32MP15_microprocessor#Part_number_codification|part number]] supports up to 800 MHz, ensure that the VDDcore minimum '''voltage''' is increased from 1.2V to 1.35 V while running above 650 MHz}}
  +
 
  +
===OPP table===
  +
At boot time, TF-A automatically selects the '''fastest''' operating point that is suitable for the current [[STM32MP15_microprocessor#Part_number_codification|part number]] according to the OPP table ('''frequency''' and '''voltage''' couples) defined in the SOC extension device tree ({{CodeSource | TF-A | fdts/stm32mp15xa.dtsi}} or {{CodeSource | TF-A | fdts/stm32mp15xd.dtsi}}).<br>
  +
At runtime, the Linux will automatically switch between the available operating points according to the CPU load and thanks to Linux cpufreq framework, configured with "ondemand" governor policy (see {{CodeSource | Linux kernel | Documentation/admin-guide/pm/cpufreq.rst}}). This feature is called dynamic voltage and frequency scaling (DVFS).<br>
  +
 
  +
For instance, in the example below, two operating points ([800 MHz ; 1.35 V]; [400 MHz ; 1.2 V]) are defined for a 800 MHz capable part number (opp-supported-hw = <0x2>), so TF-A will apply the [800 MHz ; 1.35 V] configuration at boot time and Linux will then dynamically jump between the two operating points ([800 MHz ; 1.35 V]; [400 MHz ; 1.2 V]) depending on the CPU load.
 
<syntaxhighlight lang="c">
 
<syntaxhighlight lang="c">
cpu0_opp_table: cpu0-opp-table {
+
&cpu0_opp_table {
compatible = "operating-points-v2";
 
opp-shared;
 
 
 
opp-650000000 {
 
opp-hz = /bits/ 64 <650000000>;
 
opp-microvolt = <1200000>;
 
opp-supported-hw = <0x1>;
 
};
 
 
opp-800000000 {
 
opp-800000000 {
 
opp-hz = /bits/ 64 <800000000>;
 
opp-hz = /bits/ 64 <800000000>;
Line 28: Line 29:
 
opp-supported-hw = <0x2>;
 
opp-supported-hw = <0x2>;
 
};
 
};
};
+
opp-400000000 {
  +
opp-hz = /bits/ 64 <400000000>;
  +
opp-microvolt = <1200000>;
  +
opp-supported-hw = <0x2>;
  +
opp-suspend;
  +
};
  +
};
 
</syntaxhighlight>
 
</syntaxhighlight>
 
Notes:
 
Notes:
* The operating point supported by devices supporting above 650 MHz (and up to 800 MHz) is identified by the '''opp-supported-hw''' property set to 0x2.
+
* The operating point(s) supported by devices able to run above 650 MHz (and up to 800 MHz) is/are identified by the '''opp-supported-hw''' property set to 0x2.
* This same OPP table must also be present in the Linux SOC device tree {{CodeSource | Linux kernel | arch/arm/boot/dts/stm32mp157c.dtsi}}.
+
* This same OPP table must be present in both the TF-A and Linux device tree
* It is possible to do a mix, specifying the PLL1 configuration (without an OPP table) in the TF-A device tree, whereas Linux uses the OPP table to increase the CPU frequency, once started.
 
 
* This description is valid for cold boot, but also when coming back from [[Power overview|Standby]] low power mode.
 
* This description is valid for cold boot, but also when coming back from [[Power overview|Standby]] low power mode.
 
* During cold boot, TF-A computes and saves the PLL1 settings for all operating points available in the device tree in compliance with the hardware capabilities. These saved paramaters are used later to increase the performance of the system-state transitions.
 
* During cold boot, TF-A computes and saves the PLL1 settings for all operating points available in the device tree in compliance with the hardware capabilities. These saved paramaters are used later to increase the performance of the system-state transitions.
   
===For {{EcosystemRelease | revision=1.1.0 | range=and before}}===
+
===PLL1 static configuration===
The Cortex-A7 core frequency is selected at boot time, by the FSBL (TF-A), following the [[Clock device tree configuration - Bootloader specific]] syntax. The frequency is set to 650 MHz by default, as shown in [[STM32MP15 clock tree]]. This configuration is set in the TF-A device tree, for instance {{CodeSource | TF-A | fdts/stm32mp157a-dk1.dts}}  file for STM32MP157C-DK1 board.<br>
+
The Cortex-A7 core frequency is selected at boot time, by the FSBL (TF-A), following the [[Clock device tree configuration - Bootloader specific]] syntax.<br>
 
<syntaxhighlight lang="c">
 
<syntaxhighlight lang="c">
 
&rcc {
 
&rcc {
Line 51: Line 57:
 
</syntaxhighlight>
 
</syntaxhighlight>
 
The user can reduce this frequency by changing the above configuration, either manually or via the  [[STM32CubeMX]] graphical user interface that allows generation of the corresponding device tree file.
 
The user can reduce this frequency by changing the above configuration, either manually or via the  [[STM32CubeMX]] graphical user interface that allows generation of the corresponding device tree file.
  +
<br>
  +
Notes:
  +
* The VDDcore voltage is specified in the '''regulators''' node of the board device tree, and it has to be kept consistent with the selected frequency, as explained in the [[#Overview|overview]] above.
  +
* When the PLL1 static configuration is used, TF-A ignores the OPP table (see previous chapter) that may also be present in the device tree, so the secure monitor won't be able to answer to any upcoming frequency switch from Linux. It is therefore recommended to keep only one OPP in the table given to Linux, corresponding to the frequency setup by TF-A at boot time.
   
  +
==Dynamic voltage and frequency scaling (DVFS) caution==
  +
* As stated above, as soon as at least two operating points are defined in the OPP table, Linux kernel will automatically switch between them at runtime thanks to Linux cpufreq framework, configured with "ondemand" governor policy (see {{CodeSource | Linux kernel | Documentation/admin-guide/pm/cpufreq.rst}}). It is important to notice that cpufreq framework is only monitoring the CPU load to select the OPP because this can lead to some limitation during use cases where the CPU is not loaded a lot but high reactivity is needed to respect some real time constraints, like interrupt management. If you face some system issue where the CPU reactivity may be the root cause whereas DVFS is enabled, consider doing a trial with "performance" governor (see {{CodeSource | Linux kernel | Documentation/admin-guide/pm/cpufreq.rst}}).
  +
* Selecting OPP frequencies that can be reached with [[RCC internal peripheral|RCC]] MPUDIV dividor and without configuring again the PLL1 is recommended in order to get the fastest switch time between the OPP.
 
<noinclude>
 
<noinclude>
 
[[Category:How to customize software]]
 
[[Category:How to customize software]]
 
{{PublicationRequestId | 14900 | 2020-02-11 | AnneJ}}
 
{{PublicationRequestId | 14900 | 2020-02-11 | AnneJ}}
 
</noinclude>
 
</noinclude>