BSEC internal peripheral

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1 Article purpose[edit source]

The purpose of this article is to

briefly introduce the BSEC peripheral and its main features
indicate the level of security supported by this hardware block
explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
explain, when necessary, how to configure the BSEC peripheral.

2 Peripheral overview[edit source]

The BSEC peripheral is used to control an OTP (one time programmable) fuse box, used for on-chip non-volatile storage for device configuration and security parameters.

2.1 Features[edit source]

Refer to STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to see which features are implemented.

2.2 Security support[edit source]

The BSEC is a secure peripheral.

3 Peripheral usage and associated software[edit source]

3.1 Boot time[edit source]

The BSEC is configured at boot time to set up platform security.

3.2 Runtime[edit source]

3.2.1 Overview[edit source]

The BSEC instance is a system peripheral and is controlled by the Arm^® Cortex^®-A7 secure.

3.2.2 Software frameworks[edit source]

Domain	Peripheral	Software frameworks			Comment
Domain	Peripheral	Cortex-A7 secure (OP-TEE)	Cortex-A7 non-secure (Linux)	Cortex-M4 (STM32Cube)	Comment
Security	BSEC	OP-TEE BSEC driver	Linux NVMEM framework

3.2.3 Peripheral configuration[edit source]

The configuration is applied by the firmware running in a secure context.

This configuration is done in TF-A or in OP-TEE.

3.2.4 Peripheral assignment[edit source]

Internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

☐ means that the peripheral can be assigned (☑) to the given runtime context.
✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain	Peripheral	Runtime allocation				Comment
Domain	Peripheral	Instance	Cortex-A7 secure (OP-TEE)	Cortex-A7 non-secure (Linux)	Cortex-M4 (STM32Cube)	Comment
Security	BSEC	BSEC	✓	✓