Difference between revisions of "STM32MotorControl:Single Shunt Phase Shift"

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m (Escoda Michael moved page STM32 MC Single Shunt Phase Shift to STM32MotorControl:Single Shunt Phase Shift without leaving a redirect)
 


1 Single shunt phase shift overview[edit]

In the context of a single shunt topology, the purpose of the phase-shifting is to shift one or two duty cycles to be able to sample the current signal in the boundary zones instead of inserting a distortion window.

The benefits are:

  • Fewer commutations
  • Less switching losses


2 Phase shift principle[edit]

Boundary zone 1:

  • The firmware shifts on the right the smallest duty cycle by TMIN (minimum window time for sampling)
STM32 MC Image 008.png


Boundary zone 2:

  • The firmware shifts on the right the most middle duty cycle by TMIN (minimum window time for sampling)
STM32 MC Image 009.png


Boundary zone 3:

  • The firmware shifts on the right the smallest duty cycle and on the left the highest duty cycle by TMIN (minimum window time for sampling)
STM32 MC Image 010.png


3 Peripheral usage[edit]

Phase-shifting needs the following peripherals to create the shifting. According to the advanced timer capabilities, one or two DMA channels will be used

MCU TIM DMA IRQ
F0 TIM1 DMA1_Ch5 DMA1_Ch4 DMA1_Ch5 HT and TC
G0 TIM1 DMA1_Ch4 DMA1_Ch4 HT and TC
F3 TIM1 DMA1_Ch4 DMA1_Ch4 HT and TC
TIM8 DMA1_Ch2 DMA1_Ch2 HT and TC
F4 TIM1 DMA2_stream4 DMA2_stream5 DMA_stream5 HT and TC
TIM8 DMA2_stream7 DMA2_stream1 DMA_Stream1 HT and TC
G4 TIM1 DMA1_Ch1 DMA1_Ch1 HT and TC
TIM8 DMA2_Ch1 DMA2_Ch4 HT and TC
L4 TIM1 DMA1_Ch4 DMA1_Ch4 HT and TC
TIM8 DMA2_Ch2 DMA2_Ch2 HT and TC
F7 TIM1 DMA2_stream4 DMA2_Stream4 HT and TC
TIM8 DMA2_stream7 DMA2_Stream7 HT and TC

4 Single shunt phase shift scheduling example[edit]

6 channels advanced timer and execution rate = 1 (G0,G4,F3,L4,F7)

STM32 MC Image 016.png

5 Single shunt phase shift in the STM32 MC SDK[edit]

Single shunt is implemented by r1_ps_pwm_fdbk.c (and .h) processed when the STM32 MC project uses a MCU.



{{DISPLAYTITLE: STM32 MCSDK Single Shunt Phase Shift (new in V5.Y)}}

=== Single shunt phase shift overview ===

In the context of a single shunt topology, the purpose of the phase-shifting is to shift one or two duty cycles to be able to sample the current signal in the boundary zones instead of inserting a distortion window.

The benefits are:
* Fewer commutations
* Less switching losses<!-- /* to be measured  */
* Less acoustical noise
* Better current shape
-->

<!-- /* graphics has to be remake */
=== Single shunt phase shift comparison ===

[[file:STM32_MC_Image_006a.png|right]]
* Single shunt with distortion window
[[file:STM32_MC_Image_006a.png|right]]<br clear=all>

* Single shunt with phase shift
[[file:STM32_MC_Image_006a.png|right]]<br clear=all>


* and Three shunts<br clear=all>

-->

=== Phase shift principle ===

Boundary zone 1:
* The firmware shifts on the right the smallest duty cycle by TMIN (minimum window time for sampling)  
[[file:STM32_MC_Image_008.png|right]]
<br clear=all>

Boundary zone 2:
* The firmware shifts on the right the most middle duty cycle by TMIN (minimum window time for sampling) 
[[file:STM32_MC_Image_009.png|right]]
<br clear=all>

Boundary zone 3:
* The firmware shifts on the right the smallest duty cycle and on the left the highest duty cycle by TMIN (minimum window time for sampling) 
[[file:STM32_MC_Image_010.png|right]]
<br clear=all>

=== Peripheral usage ===

Phase-shifting needs the following peripherals to create the shifting. According to the advanced timer capabilities, one or two DMA channels will be used 

{|
|-
! MCU !! TIM !! DMA !! IRQ
|-
| F0 || TIM1 || DMA1_Ch5 DMA1_Ch4 || DMA1_Ch5 HT and TC
|-
| G0 || TIM1 || DMA1_Ch4 || DMA1_Ch4 HT and TC
|-
| F3 || TIM1 || DMA1_Ch4 || DMA1_Ch4 HT and TC
|-
| || TIM8 || DMA1_Ch2 || DMA1_Ch2 HT and TC
|-
| F4  || TIM1 || DMA2_stream4 DMA2_stream5 || DMA_stream5 HT and TC
|-
| || TIM8 || DMA2_stream7 DMA2_stream1 || DMA_Stream1 HT and TC
|-
| G4 || TIM1 || DMA1_Ch1 || DMA1_Ch1 HT and TC
|-
| || TIM8 || DMA2_Ch1 || DMA2_Ch4 HT and TC
|-
| L4 || TIM1 || DMA1_Ch4 || DMA1_Ch4 HT and TC
|-
| || TIM8 || DMA2_Ch2 || DMA2_Ch2 HT and TC
|-
| F7 || TIM1 || DMA2_stream4 || DMA2_Stream4 HT and TC
|-
| || TIM8 || DMA2_stream7 || DMA2_Stream7 HT and TC
|}

=== Single shunt phase shift scheduling example ===

6 channels advanced timer and execution rate = 1 (G0,G4,F3,L4,F7)
[[file:STM32_MC_Image_016.png|center]]

=== Single shunt phase shift in the STM32 MC SDK ===

Single shunt is implemented  by r1_ps_pwm_fdbk.c (and .h) processed when the STM32 MC project uses a MCU.
<noinclude>


[[Category:Motor Control]]

{{PublicationRequestId|19719| 4/22/2021| JM LAGOUTTE}}<noinclude>

<!--
Internal source: "to be completed" VX.0
-->
(No difference)